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L2 Cache Latency Guide Posted!

A

Adrian Wong

Member
Hello everyone!

Adrian's Rojak Pot has just posted the L2 Cache Latency guide! Here's a clip of the guide :-

"In this article, we will be testing all 15 different L2 cache latencies in order to determine their effect on performance. Optimizers would be interested in just how much performance increases from the reduction of the L2 cache latency. Overclockers, on the other hand, would be interested to know the degree of performance degradation when using a higher L2 cache latency because that will help them determine if the increase in clockspeed made possible by the higher L2 cache latency is worth the loss in L2 cache performance.

But whatever the reasons are, I'm sure you will agree that it would be more than a little interesting to see how those 15 cache latencies fare against each other. So, let's move on now to the benchmarks and their results!"

Adrian Wong
Adrian's Rojak Pot
 
Doesn't your article just apply to older CPUs?

I've read on the threads that with CPUs like the celeron IIs you can't alter the latency.

Am I correct?
 
I posted in the other thread but the answer is yes, P3s/C2 TBIRD/Duron can not have the latency changed. H. Odas proggie still measures some value in a hardware register to report latency. At some point in time on some generation of processor this was correct but it doesn't apply today.
 
Hello ingenue007,

That's right. The L2 cache latency of new processors can't be changed. That's what I stated in the article as well. Really unfortunate. But if you own a Pentium II or a Celeron (not with a Coppermine core), then L2 cache latency adjustment is still a valid option.

Adrian Wong
Adrian's Rojak Pot
 
I still don't believe that the Latency Values specified have any REAL effect. If 1 is fastest and 15 in slowest, this would translate in cycles added between the L1 miss and the L2 request. The results would be very predictable. Latency too low and the comparators for the cache would not have time to determine a 'hit' or miss. They would not be effected by ECC. Remember, the comparator determines a hit or miss through the Cache TAG.
 
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