L1 & L2 Cache

[rodan]

I noticed the new AMD Athlon Thunderbird(Socket A) cpu has more L1 cache on it, than previous AMD Athlon Classic(Slot 1)..... Question: is more L1 cache better than more L2 cache on the chip? Looks like they have taken the L2 cache down from the 512k, and increased the L1 cache to 384k.

 

[Sunner]

It has the same amount of L1 as the Athlon classic(128 KB).
The difference is it has 256 KB of onchip exclusive L2 cache, and since its exclusive, data doesnt have to be replicated from the L1 to the L2, making it 384 KB alltogether.

But they're still separate caches, with different properties, so its in no way the same thing as having 384 KB of L1.

 

[Whitedog]

It's true. I've seen some confusing adds about the new AMD chips..

The real facts:

Classic Althon
L1 Cache - 128K
L2 Cache - 512K
Total = 640K

Thunderbird
L1 Cache - 128K
L2 Cache - 256K
total = 384K

Duron
L1 Cache - 128K
L2 Cache - 64K
total = 192K

Piii Copperhead
L1 cache - 32K
L2 cache - 256K
Total = 288K

Celetron
L1 cache - 32K
L2 cache - 128K
Total = 160K

 

[judgebao]

I'm just wondering for Tbird / Cumine. If L1 and L2 cache have the same speed (core speed). Why would it need to be separated? Why not just make 1 cache. 🙂

 

[Vegito]

The celeron cache total is 160 but the difference is inclusive cache and exclusive cache..

I forgot which has which but for celerons, everything in L1 is in L2 thus L2 is actually smaller. & Durons actually have two seperate cache in that L1 stores it's on and L2 stores other data..

 

[DaddyG]

The L1 cache has a lower latency than L2 on both Athlon and Peeee3's

 

[Goi]

Some confusing advertising there, but here's the low down

All Athlons/Durons have 128KB(64KB instruction/64KB data) of on-die L1 cache. The difference is in the L2 cache.

The classic Athlons(both 0.25u K7 and 0.18u K75 cores) have 512KB of off die, on package L2 cache, which I believe is 8-way set associative.

The Thunderbirds have 256KB of on-die 16-way set associative L2 cache on a 64-bit cache line.

The Durons have 64KB of on-die 16-way set associative L2 cache on a 64-bit cache line.

Thunderbirds and Durons use exclusive cache, in that data in doesn't have to be replicated in both L1 and L2 cache. It either exists in 1 level, the other, or none - never both. These increases effective cache size, and hence cache hit rate.

All P2,P3 and Celerons have the same 32KB(16KB instruction/16KB data) of on-die L1 cache.

Klamath, Deschutes and Katmai P2/P3 processors had 512KB off-die, on package L2 cache. I forgot the associativity.

Coppermine P3s have 256KB on-die 8-way set associative L2 cache on a 256-bit cache line.

Covington Celerons didn't have any L2 cache at all.

Mendocino Celerons has 128KB on-die 4-way set associative L2 cache on a 64-bit cache line.

Coppermine-128 Celerons has 128KB on-die 4-way set associative L2 cache on a 256-bit cache line.

And that's about it. There are other differences in cache hierarchy, but these are the more important ones.

 

[Sunner]

Klamath's cache is 4 way associative.

 

[BurntKooshie]

Whitedog
A correction:

Classic Althon
L1 Cache - 128K
L2 Cache - 512K

Cache is INCLUSIVE

Total = 512-128 = 384 ondie cache effective

Thunderbird
L1 Cache - 128K
L2 Cache - 256K

(cache is exclusive)

256 + 128 = 384K effective


Duron
L1 Cache - 128K
L2 Cache - 64K

(cache is exclusive)

128 + 64 = 192K effective

Piii Coppermine
L1 cache - 32K
L2 cache - 256K

32 + 256 (inclusive) = 256k (effective)

Total = 288K

Celetron
L1 cache - 32K
L2 cache - 128K

32 128 (inclusive) = 128k (effective)


Inclusive means that data in the L1 is duplicated in the L2. Exclusive means that data in L1 is NOT duplicated in the L2, therefore you can simply add the two caches.

 

[MadRat]

BurntKooshie beat me to it!

Athlon Classic has associative cache.

ps - this new JAVA crap "looks suck" in 1024x768 mode. 🙁

 

[Sunner]

<< &quot;Total = 512-128 = 384 ondie cache effective&quot; >>



BurntKooshie, the classic doesnt have ondie cache.

 

[utopia]

Come down people...

AMD Classic Athlon
L1 Cache - 128K
L2 Cache - 512K

inclusive cache
512-128 = 384 offdie (1/2 or 3/5 of core clock) cache effective



AMD Thunderbird
L1 Cache - 128K
L2 Cache - 256K

exclusive cache
256 + 128 = 384K on-die (core clock) effective cache


AMD Duron
L1 Cache - 128K
L2 Cache - 64K

exclusive cache, just like the big bro Tbird.
128 + 64 = 192K on-die (core clock) effective cache


Intel PIII Katmai
L1 cache - 32K
L2 cache - 512K (off die, 1/2 clock core)

(inclusive) 512K (effective)


Intel PIII Coppermine
L1 cache - 32K
L2 cache - 256K

32 + 256 (inclusive) = 256k (core clock) (effective)


Intel Celeron FCPGA
L1 cache - 32K
L2 cache - 128K

(inclusive) = 128k (effective)


thats about it...