Can't overclock memory without overclocking CPU unless you lower the multiplier. Memory speed is derived from CPU clock. The smallest possible divider (highest memory speed) is ALWAYS equal to the CPU multiplier. For example, for a CPU mult of 11, the minimum divider (used for 200MHz setting) is 11, 2200/11=200. You need to lower the CPU multiplier while overclocking FSB if you want to overclock memory without overclocking CPU Also, OCZ Gold Rev 3. is 466 stock but may get up to 533. Thats would be 233fsb/2566cpu or 266fsb/2933cpu at your default multi of 11. 2566 is doable but 2933 seems like a stretch. If you planned on running memory too much higher than 233MHz, I think you are paying for a higher multi than you need (assuming that a 3200+ or 3000+ is capable of the same overclocks as the 3500+). Also, as jpeyton says, lower the LDT ratio from 5x to 4x if you are overclocking to <= 250 fsb. If you go over 250 fsb, you may need to lower the LDT ratio again to 3x. You should keep FSBxLDT under 1000 if you are testing to see how far you memory and CPU go.
Regarding memory latency, it all depends on what the total latency for the address to get out and the data to get back in to the CPU core. I'm not familiar with these characteristics but the info must be out there. For example, if you are talking about CL2.5 vs CL3 that is 1 clock tick at 200MHz or 4 nanoseconds. If the total latency through the memory and the memory controller is significantly more than this, increasing the FSB speed (memory and memory controller speed) should more than make up for increasing the CL from 2.5 to 3 because each clock tick is that much shorter. For example say we have 50ns latency back and forth through the memory controller. Difference between CL2.5 and CL3 is 2.5 ns. If you increase to CL3 that changes latency to 55ns, but if you also change FSB to 233, the total latency is reduced to ~47 ns.
Actually, my guess for memory latency doesn't seem to be that far off according to
http://www.xbitlabs.com/articl...y/athlon64-3200_6.html
90 CPU cycles is ~41ns and 103 CPU cycles is ~47 ns. That change of I would expect increasing CL by .5 and RCD by 1 increases latency by about 7.5 ns (not far off). If a majory of the latency reported in this article is in the memory and memory controller, I would suspect that upping the fsb to 250 ~ 266 will more than make up for looser timing.