ITT: We speculate on Skylake E5 and E7 Core counts, memory channels, SATA ports, etc

[imported_ats]

Each Xeon-D dies is 160mm2 on 14nm. This includes eight Broadwell cores, 12MB L3 Cache, 24 PCIe 3.0lanes, two channel DDR4 memory controller, two channel DDR3 memory controller, networking controller (two 10GbE), four usb 3.0.

Xeon-D supports DDR4 only. And even Haswell-EX which supports both DDR3/4 only one 2 memory controllers both of which support DDR3/4.

 

[frozentundra123456]

Just to add some info to this thread, here is the history of Intel x86 core count progression (top die size)

65nm: dual core (quad cores were two dual cores on package)
45nm: quad core
32nm: octocore
22nm: eighteen cores

Amazingly Intel has at least doubled core count* with every node and I don't expect to see this change with 14nm.

*32nm to 22nm transition was actually 125% increase in core count, rather than merely double (ie, 100% increase).

Too bad none of this has filtered down to a mainstream desktop hex core. Through all this, we have been stuck on quad.

 

[cbn]

You have to add uncore space for that. If you base on this,

684mm2/2 x 1.25 cores = 427mm2, but ended up 513mm2
513mm2/2 x 1.8 cores = 462mm2, but ended up 664mm2

Take a look at this picture: http://www.anandtech.com/show/9193/the-xeon-e78800-v3-review

By my calculations, 18C Haswell (278mm2) with 45MB of L3 cache (~146mm2) comes out to be ~424mm2 .

Since the total die size is 662 mm2 for 18C Haswell -EP/-EX that leaves 238mm2 for the components beyond the cores and L3 cache.

Or another way of looking at things: The components beyond cores and L3 cache for the 18C Haswell -EP/-EX comprise 35% of the die.

P.S. Not sure why going from Nehalem-EX to Westmere-EX didn't scale well. Maybe the 45nm to 32nm node transition wasn't true 2 to 1 scaling? (32nm was a fast clocking node and maybe Intel decided to make the metal layers less dense than they normally would have?) As far as scaling from 10C Westmere to 18C Haswell goes, those were different platforms (ie, more variables for that comparison making the scaling issue more difficult to assess)

 

[cbn]

Xeon-D supports DDR4 only. And even Haswell-EX which supports both DDR3/4 only one 2 memory controllers both of which support DDR3/4.

According to the following article from PCPer, Xeon-D does have both DDR3 and DDr4 memory controllers. (the DDR3 is disabled as we don't see it on any of the current SKUs)

http://www.pcper.com/news/Editorial...ocessors-Aimed-Low-Power-High-Density-Servers

EDIT: If DDR3 and DDR4 are combined into one controller, wouldn't having a memory controller specialized for just DDR4 be smaller than one that is capable of both DDR3 and DDR4?

 

[cbn]

You cant produce 1000mm2 because its not possible with the current process and tools. The upper limit is around 800mm2 or something.

Why do you think 40C Skylake would be 1000 mm2?

As mentioned previously in post #28, my calculation of the components besides cpu cores and L3 cache on the Haswell 18C amounts to only 35% of the die. See picture below for a visual of that:

.....And since Intel got a really good density increase going from 22nm to 14nm on the cores and L3 cache for Broadwell, I would expect the rest of the processor to also benefit from the reduction in die area.

So for a hypothetical Broadwell 40C (with 100MB L3 cache) using the exact same "other parts" as a Haswell 18C (ie, 40 PCIe lanes, quad channel memory controller) the final die size would ~572mm2. See below for calculations:

465mm2 for 40 broadwell cores with 100MB L3 cache (see post #22) + 107 mm2 for the rest of the processor including 40 PCIe lanes, quad channel memory controller (see post #28 for the 238 mm2 die estimate for "parts of 18C Haswell beyond cores and L3 cache" which would be ~2.23 times greater in size than if were shrunk to 14nm (see post #23), so 238 mm2 * 1/2.23= 107 mm2).

With that mentioned, I would think a 40C Broadwell would need more than four memory channels so this hypothetical processor will never exist. But it is interesting to think of the possibilities of what could happen on the next platform.

How much die increase will a Skylake core add over a Broadwell core ? How much die increase would a eight channel memory add? Will Intel increase the cache per core?

 

[IntelUser2000]

465mm2 for 40 broadwell cores with 100MB L3 cache (see post #22) + 107 mm2 for the rest of the processor including 40 PCIe lanes, quad channel memory controller (see post #28 for the 238 mm2 die estimate for "parts of 18C Haswell beyond cores and L3 cache" which would be ~2.23 times greater in size than if were shrunk to 14nm (see post #23), so 238 mm2 * 1/2.23= 107 mm2).

You can't assume that. Uncores, Cores, Caches all have different scaling factors.

Also, I just found out the core sizes on the Core M chip and the Core i3/i5/i7 15/28W chips are different. The Core M cores are ~7mm2 and the latter turns out to be 8.2mm2. The reason is likely because Core M is using 14nm SoC process and 15W/28W ones use regular process. Xeon D is likely using the SoC process.

The shared L3 cache blocks on Core M are 6.6mm2 and Core ix are 7.2mm2. The System Agent section is 11.82mm2 on the former and 12.41mm2 on the latter.

That means while there is a density advantage, there is a significant clock speed sacrifice. Because Xeon EP and EX chips have high-frequency counterparts and they are all derivatives from the same die, it means they need to all use the regular process, not the slower and denser SoC one.

New math: 328mm2 for 40 cores, 180mm2 for 100MB L3 = 508mm2, or ~510mm2.

And you need to add the Uncore. And its the least scalable part of the chip. Haswell's 2 channel memory controller is 10.7mm2. Broadwell is nearly 8mm2. I highly doubt the Uncores would scale better than to be 60% of the size. And the Uncores have to be further larger because it has to support more cores. 60% scaling with Uncore means 143mm2 or total of 653mm2.

I also doubt they would make something much larger than 700mm2 anyway. The much lower volume Knights Landing is supposedly 720mm2.

If the size is ok, power won't be. So there is no reason for them to put in 40 cores either way.

Couple of reasons why what you are proposing won't happen:
1. Power, power power. Too much power for 40 cores
2. Die sizes are way too large for a "Tick".

Nehalem EX - 45nm 8 cores. 684mm2
Westmere EX - 32nm 10 cores. 513mm2
Ivy Bridge EX - 22nm 15 cores, 541mm2
Haswell EX - 22nm 18 cores. 664mm2

Tick = Smaller Die, Tock = Bigger die

What happens to Skylake EX if Broadwell EX already turns out to be 700mm2? Are they going to put 54 cores on the same 14nm process? Simply put Broadwell EX has to be in the ~500mm2 range.

 

[Fjodor2001]

65nm: dual core (quad cores were two dual cores on package)
45nm: quad core
32nm: octocore
22nm: eighteen cores

Mainstream desktop equivalent:

65nm: quad core
45nm: quad core
32nm: quad core
22nm: quad core
14nm: quad core

Sad but true...

 

[IntelUser2000]

My prediction:

Broadwell EP/EX: 24 cores

Total: 512mm2
24 cores: 197mm2
60MB L3: 110mm2
Rest: 205mm2

Then with Skylake they'll have room to expand and get it back to 65xmm2+ range.

Sad but true...

As always follow the money.

 

[CHADBOGA]

Mainstream desktop equivalent:

65nm: quad core
45nm: quad core
32nm: quad core
22nm: quad core
14nm: quad core

Sad but true...

Not sure quad core was mainstream when Intel was on 65nm.

 

[NTMBK]

Not sure quad core was mainstream when Intel was on 65nm.

Q6600 was pretty mainstream, no?

 

[ShintaiDK]

Q6600 was pretty mainstream, no?

Not really. In todays prices a Q6600 would cost 625-960$ depending on when you look at it in its lifespan.

 

[ShintaiDK]

Why do you think 40C Skylake would be 1000 mm2?

As mentioned previously in post #28, my calculation of the components besides cpu cores and L3 cache on the Haswell 18C amounts to only 35% of the die. See picture below for a visual of that:

Your calculation is wrong because you forget the scaling issue with more cores. Also shown as previous examples from older CPUs.

 

[CHADBOGA]

Q6600 was pretty mainstream, no?

Wasn't it over $800 when it was first released?

 

[Fjodor2001]

Not really. In todays prices a Q6600 would cost 625-960$ depending on when you look at it in its lifespan.

Back then all CPUs were more expensive. The Q6600 was definitely considered mainstream if you look at the volumes it sold in among desktop computers.

 

[cbn]

Also, I just found out the core sizes on the Core M chip and the Core i3/i5/i7 15/28W chips are different. The Core M cores are ~7mm2 and the latter turns out to be 8.2mm2. The reason is likely because Core M is using 14nm SoC process and 15W/28W ones use regular process. Xeon D is likely using the SoC process.

The shared L3 cache blocks on Core M are 6.6mm2 and Core ix are 7.2mm2. The System Agent section is 11.82mm2 on the former and 12.41mm2 on the latter.

So Core M and the Broadwell 15W/28W have a different die size then. Do have a link for that?

P.S. I tried doing some measurements using the following picture of Core M (Left), Broadwell ULT (middle), Haswell ULT (right), but couldn't find a difference in size (at the points I measured) between Core M and Broadwell ULT:

 

[Enigmoid]

I think he is making a measurement error. Core M and GT2 U level chips should be identical.

 

[IntelUser2000]

I think he is making a measurement error. Core M and GT2 U level chips should be identical.

No I am not. Take the pictures and the die sizes and that's what you get. It was also pointed out in an article by Ashraf that Xeon D is quite small, and its likely due to the SoC process. It also makes sense Core M is small as well.

So Core M and the Broadwell 15W/28W have a different die size then. Do have a link for that?

You missed the whole point that if they make Broadwell too large, they'd have no room for Skylake, and the Core scaling never follows 14/22 squared. They have never done Xeon processors that are 700mm2, why do you think it'll change now? Low volume processors like Xeon Phi and Itanium are different.

 

[imported_ats]

EDIT: If DDR3 and DDR4 are combined into one controller, wouldn't having a memory controller specialized for just DDR4 be smaller than one that is capable of both DDR3 and DDR4?

Not in any meaningful way. DDR3 is basically a full subset of DDR4. The primary differences are in timing parameters and a couple more command options/restriction for DDR4 vs DDR3. Complete noise area wise at best, realistically zero difference.

 

[cbn]

It was also pointed out in an article by Ashraf that Xeon D is quite small, and its likely due to the SoC process.

I touched on the Xeon-D density issue in this post:

http://forums.anandtech.com/showpost.php?p=37362810&postcount=20

Long story short: differences in cache (12mb L3 vs. 4MB L3) confound a direct density comparison of Xeon-D to Broadwell U.

Furthermore, Xeon-D can turbo to 2.5 Ghz on all cores. Therefore I suspect the 1C turbo is limited to 2.6 Ghz strictly for product segmentation purposes.

In a nutshell, I believe Xeon-D has the same core as Broadwell U.

You missed the whole point that if they make Broadwell too large, they'd have no room for Skylake

Yes, I don't believe there would be Broadwell 40C (re: quad channel memory would not be enough for 40C. See post #30)

Also like you mentioned, the die would be too large for a 14nm Tic.

But if Skylake moved on to eight channel memory then there is plenty memory bandwidth to fill out the die with more cores on 14nm Toc.....and add even more cores on the 10nm Tic.

P.S. As far as power goes Intel could always lower clocks on 40C Skylake and/or increase TDP.

 

[Enigmoid]

No I am not. Take the pictures and the die sizes and that's what you get. It was also pointed out in an article by Ashraf that Xeon D is quite small, and its likely due to the SoC process. It also makes sense Core M is small as well.

Core M and Broadwell U GT2 are both 1.3 B transistors and 82 mm^2.

 

[Arachnotronic]

Core M and Broadwell U GT2 are both 1.3 B transistors and 82 mm^2.

They're the same exact die.

 

[Enigmoid]

They're the same exact die.

Yep. Thats why his other measurements are erroneous.

 

[Arachnotronic]

Mainstream desktop equivalent:

65nm: quad core
45nm: quad core
32nm: quad core
22nm: quad core
14nm: quad core

Sad but true...

They added a lot of functionality in the iGPU, though.

 

[IntelUser2000]

They're the same exact die.

Core M

http://www.extremetech.com/wp-content/uploads/2014/09/intel-core-m-broadwell-y-die-diagram-map.jpg

1169 x 528 617232 = 82mm2

165 x 319 52635 = 6.9mm2


Core i3/i5/i7

http://blogs-images.forbes.com/patrickmoorhead/files/2015/01/5th-gen-core.png

1620 x 567 918540 = 133mm2

162 x 345 55890 = 8.09mm2

Update:

http://www.cdrinfo.com/images/uploaded/Intel_broadwell_1.jpg

When you calculate the 2 dies there, the GT2 part comes out to be ~7mm2 and the GT3 part 8mm2 for the cores.

The weird thing I noticed, and which would make me inaccurate is the empty spot which the Intel presentation are also counting as cores that does not exist on the GT2 die.

I touched on the Xeon-D density issue in this post:

http://forums.anandtech.com/showpost...0&postcount=20

http://www.fool.com/investing/gener...oration-a-look-at-the-new-xeon-d-process.aspx

According to Intel, the Broadwell-U 2+3 configuration features 1.9 billion transistors and fits into an area of 133 square millimeters. This implies a density of approximately 14.3 million transistors per millimeter squared.

SemiAccurate reported that the Xeon D die weighs in at 160 square millimeters. Intel, in a recent post on Twitter, said its Xeon D processor is made up of 4.3 billion transistors -- implying a transistor density of approximately 26.88 million transistors per square millimeter.

Its unfortunate Intel does not reveal the actual die, except one featured on the hand. What Ashraf is implying on his article makes complete sense. And Xeon D is also System on a Chip, which would use System on a Chip, or SoC process.

 

[cbn]

The weird thing I noticed, and which would make me inaccurate is the empty spot which the Intel presentation are also counting as cores that does not exist on the GT2 die.

Yep, the iGPU and system agent on the GT3 die has that empty spot too:

(I wonder why that empty spot exists?)

P.S. Thanks for bringing this up. I totally forgot about the GT3 die.