Originally posted by: ken008
MMX instuctions were barely used because they were hard for the programer to implement. SSE2 may suffer from the same problem.
SSE2 was already implemented, and it gave GREAT advantages to the P4. However, once n got to 498xxx or something, there was a bug that caused any SSE2 enabled CPUs to crash out. This is why 1.1.1 was released, disabling SSE2 for P4s and Opterons (but not Pentium-M CPUs

). Without SSE2, the P4 is crippled, hence why a much slower Athlon XP currently races waaay ahead.
Once Louis' finals are over, then he should hopefully be able to get the SSE2 bug fixed, and release another version, which will put P4s back at the top of the peformance charts
Garry