Is Intel's "Process Lead" Somewhat a Sham?

[witeken]

Intel's node naming is extremely questionable.

http://www.electronicsweekly.com/mannerisms/general/the-intel-nanometre-2013-02/

Intel 22nm FINFET transistor density was comparable to TSMC 28nm planar. Both used single patterning immersion lithography. btw Intel cannot have a major lead at 14nm as it uses dual pattern immersion litho just like TSMC/Samsung. All three have a M1 metal pitch of 64 nm. Intel's lead if any is marginal.

Intel's node naming isn't any more questionable than other foundries'. In contrary, TSMC, GlobalFoundries and Samsung will go from 20nm to 16/14nm without any meaningful increase in transistor density, which is exactly the opposite of what Moore's Law implies. If Intel's slide is correct, Intel will have a 1.5x to 1.3x (FinFET+) density advantage with 14nm for the next 2 years, which will increase even more at 10nm (certainly versus 16nm). You can have the fastest transistors in the world (which TSMC apparently claims they will have), but if you have to pay the foundry tax, don't have great yields, have expensive wafers and you run out of die area because of the lack of density improvements, you won't be competitive against a company who doesn't have all of those problems.

Where did you get the 3x power per core number ? do you have proof to back your statement.

Sure: Intel Vindicated, Very Competitive With Apple's A7.

The too long, didn't read version is that Apple simply doesn't have 3D transistors.

Cyclone is already on par or better than Ivy bridge on a clock for clock basis

http://browser.primatelabs.com/processor-benchmarks
http://browser.primatelabs.com/ios-benchmarks

Single thread integer

core i3 3217u (1800 mhz) - 1608 (64 bit score)
A7 (1400 Mhz) - 1392
Baytrail z3770 (1460 mhz, 2400 mhz turbo) - 935 (32 bit score)

Multithread performance

core i3 3217u (1800 mhz) - 3370 (64 bit score)
A7 (1400 Mhz) - 2519
Baytrail z3770 (1460 mhz, 2400 mhz turbo) - 2967 (32 bit score)

1.8 Ghz core i3 3217u (ivybridge) has a 15% higher single thread performance than 1.4 Ghz A7 (Cyclone) while running at a 28% higher clock speed . Multithread performance is 33% higher on 1.8 Ghz ivybridge primarily because ivybridge has Hyperthreading and can support 4 threads while Cyclone can only support 2 threads. Also the A7 is definitely a lower TDP part than core i3 3217u which is a 17w SKU

http://ark.intel.com/products/65697/Intel-Core-i3-3217U-Processor-3M-Cache-1_80-GHz

Intel doesn't stand still either. Anyway, I actually don't think Apple will move to Intel in the near future.

I wish we would get another review like this one, so the discussion could be more than just speculation.

Keep believing what you want to. Your illusion will be shattered in late 2015 when Broxton goes up against the Apple A9 built at either TSMC 16FF+ or Samsung 14 FINFET.

Intel has had a manufacturing lead for a lot of years now, and the economics certainly aren't getting any better for the dedicated foundries at this point of Moore's Law, so I'm very skeptical for claims that TSMC or Samsung will suddenly catch up.

 

[Khato]

High current drive means high transconductance and low Vth , for thoses unfamiliar with thoses enginering terms transconductance is the current through the device, a FET, for a given command voltage , while Vth is the command voltage at wich the device start to conduct according to a square law, that is , the current increase as a square of the command voltage, below this level the current through the device will decrease almost exponentialy as the command voltage is reduced but conduction will not be zero when the command voltage reach zero volt, a very low current will still exist through the device , this is called leakage and the lower the Vth the higher the leakage.

Now Vth is inherently a compromise, the lower the Vth the higher the possible frequency but also the leakage, the higher, to some extent, the Vth and the lower the leakage and the frequency capability so this second case is the one wich is relevant for low power devices with lower frequencies, that is what we are used in most conventional PCs CPUs but it happen that 2 cores at frequency 1.25X and voltage Y with a 80% software scaling will outperform a single core at frequency 2X and 1.4Y voltage power efficency wise so the pursuit of the highest frequencies/I drive is somewhat at odd with the current (!) industry trends..

While the above is quite correct it's useful to apply it to actual examples rather than to simply spew out technical information and leave those who read it to come to their own conclusions. Namely, in this case it is true that Intel traditionally has higher drive currents than their competition... but it's industry standard practice to report those drive currents at a given voltage and, rather than specify Vt, a specific Ioff (leakage current.) To give a somewhat dated example since the information for it is easy to find, Intel's 32nm process had Idsat, drive currents, of 1620/1370 uA/um for NMOS/PMOS at a 1V Vdd and 100 nA/um Ioff... compared to TSMC's initial 28nm process at 1360/960 for the same parameters. Which is to say that Intel had 20%/40% higher drive currents than TSMC with the exact same leakage.

That said, it does appear as though TSMC is making excellent progress in that respect with their '16nm finfet' process. In a paper to IEDM 2013 TSMC claims that they have a 16nm finfet process with drive currents of 520/525 uA/um at 0.75V Vdd and 30pA/um Ioff... which is a fair bit better than Intel's low power 22nm which is only capable of 410/370 uA/um at the same parameters... though keep in mind that Intel's 22nm process will have been out in products for somewhere in the 3-4 year range before we see products based on TSMC's '16nm finfet', so the only oddity here is that TSMC will actually be ahead of Intel's previous process for a change.

 

[Arachnotronic]

While the above is quite correct it's useful to apply it to actual examples rather than to simply spew out technical information and leave those who read it to come to their own conclusions. Namely, in this case it is true that Intel traditionally has higher drive currents than their competition... but it's industry standard practice to report those drive currents at a given voltage and, rather than specify Vt, a specific Ioff (leakage current.) To give a somewhat dated example since the information for it is easy to find, Intel's 32nm process had Idsat, drive currents, of 1620/1370 uA/um for NMOS/PMOS at a 1V Vdd and 100 nA/um Ioff... compared to TSMC's initial 28nm process at 1360/960 for the same parameters. Which is to say that Intel had 20%/40% higher drive currents than TSMC with the exact same leakage.

That said, it does appear as though TSMC is making excellent progress in that respect with their '16nm finfet' process. In a paper to IEDM 2013 TSMC claims that they have a 16nm finfet process with drive currents of 520/525 uA/um at 0.75V Vdd and 30pA/um Ioff... which is a fair bit better than Intel's low power 22nm which is only capable of 410/370 uA/um at the same parameters... though keep in mind that Intel's 22nm process will have been out in products for somewhere in the 3-4 year range before we see products based on TSMC's '16nm finfet', so the only oddity here is that TSMC will actually be ahead of Intel's previous process for a change.

The problem here is that if you improve the Intel 22nm performance #'s by 40% (as claimed at Investor Meeting) to get to the 14nm numbers, you see that TSMC 16 FF and Intel 14nm are roughly equivalent.

Hmm...

 

[jdubs03]

The problem here is that if you improve the Intel 22nm performance #'s by 40% (as claimed at Investor Meeting) to get to the 14nm numbers, you see that TSMC 16 FF and Intel 14nm are roughly equivalent.

Hmm...

16FF+ is likely to be the process that is competitive with Intel's 14nm. TSMC didn't disclose anything about Turbo, so let's just regard that as nonexistent.

 

[TuxDave]

...
In a paper to IEDM 2013 TSMC claims that they have a 16nm finfet process with drive currents of 520/525 uA/um at 0.75V Vdd and 30pA/um Ioff... which is a fair bit better than Intel's low power 22nm which is only capable of 410/370 uA/um at the same parameters...
...

This came up in an offline conversation and I brought up the question on whether or not the gate capacitance parameter was also the same. When moving from planar to finfet, you dramatically get a tighter control over the channel which you can use to significant reduce leakage and improve your drive current. However, you can also back off slightly from 100% of THAT goodness by reducing your gate capacitance: a little more leakage, a little less current, but also lower dynamic power by reducing gate capacitance.

I'm not making any conclusions, I'm just pointing out some relevant parameters which have significant meaning.

 

[Exophase]

It's interesting that porting a CPU to TSMC was deemed cheaper than porting a modem back to Intel, even with TSMC taking a cut of the profit margins. I wonder whether there is some deeper issue- that Intel can't get its wafer costs low enough to compete in the rock-bottom smartphone market where SoFIA is targeted.

But yeah, it should just be a temporary blip. Still, one of those moments that makes you wonder what on earth is going on with Intel's modems!

It's interesting but it's not really surprising. A baseband processor needs a high speed mixed signal interface to talk to the radio, Intel may have needed more time to get the same level of technology available in their fabs. Silvermont, on the other hand, wouldn't be using any very exotic sort of blocks vs any other modern CPU made at TSMC.

 

[Khato]

This came up in an offline conversation and I brought up the question on whether or not the gate capacitance parameter was also the same. When moving from planar to finfet, you dramatically get a tighter control over the channel which you can use to significant reduce leakage and improve your drive current. However, you can also back off slightly from 100% of THAT goodness by reducing your gate capacitance: a little more leakage, a little less current, but also lower dynamic power by reducing gate capacitance.

I'm not making any conclusions, I'm just pointing out some relevant parameters which have significant meaning.

Excellent point - I tend to forget about such since it's frequently not included in papers on new process technologies and I'm spared dealing with the layout side of design. But now that I think about it, wasn't one of the cons of going to finfet higher intrinsic gate capacitance? Which it would seem that Intel did something about since they report lower drive currents compared to 32nm while still improving delay times. Would also explain why Intel uses switching energy/active power in their comparison charts instead of total power.

Unfortunately such is merely a logical theory since the closest to gate capacitance that's usually reported would be delay times... and those are usually presented in such a fashion as to make comparisons difficult at best.

 

[Abwx]

While the above is quite correct it's useful to apply it to actual examples rather than to simply spew out technical information and leave those who read it to come to their own conclusions. Namely, in this case it is true that Intel traditionally has higher drive currents than their competition... but it's industry standard practice to report those drive currents at a given voltage and, rather than specify Vt, a specific Ioff (leakage current.) To give a somewhat dated example since the information for it is easy to find, Intel's 32nm process had Idsat, drive currents, of 1620/1370 uA/um for NMOS/PMOS at a 1V Vdd and 100 nA/um Ioff... compared to TSMC's initial 28nm process at 1360/960 for the same parameters. Which is to say that Intel had 20%/40% higher drive currents than TSMC with the exact same leakage.

That said, it does appear as though TSMC is making excellent progress in that respect with their '16nm finfet' process. In a paper to IEDM 2013 TSMC claims that they have a 16nm finfet process with drive currents of 520/525 uA/um at 0.75V Vdd and 30pA/um Ioff... which is a fair bit better than Intel's low power 22nm which is only capable of 410/370 uA/um at the same parameters... though keep in mind that Intel's 22nm process will have been out in products for somewhere in the 3-4 year range before we see products based on TSMC's '16nm finfet', so the only oddity here is that TSMC will actually be ahead of Intel's previous process for a change.

My point was to give an explanation not to speak real numbers and indeed as pointed by Tuxdave transconductance and Vth are not all since they define the transistor conductance law but without respect of what is to be driven , i.e, other transistors gates wich are complexe loads whose caracteristics define the transistor speed as much as its conductance if not more depending of the technology, so without knowledge of theses parameters, i.e, Spice parameters, it s impossible to extract the velocity of thoses components, that s why the Ioff and Ion although instructive because they allow to estimate gate length and channel width are neverless not enough to estimate accurately the dynamic caracteristics.

 

[witeken]

I just found out that an A15 core in the Nexus 10 uses 1.5W (measured by Intel). When I look at the Z3770 benchmarks on AnandTech, the Z3770 (0.8W) is about 50% faster. Multiply those 2 numbers and you'll find out that Silvermont has up to 3x higher performance/watt.

 

[Arachnotronic]

I just found out that an A15 core in the Nexus 10 uses 1.5W (measured by Intel). When I look at the Z3770 benchmarks on AnandTech, the Z3770 (0.8W) is about 50% faster. Multiply those 2 numbers and you'll find out that Silvermont has up to 3x higher performance/watt.

The Nexus 10 was released in 2012, so this is a completely unfair comparison.

 

[Khato]

The problem here is that if you improve the Intel 22nm performance #'s by 40% (as claimed at Investor Meeting) to get to the 14nm numbers, you see that TSMC 16 FF and Intel 14nm are roughly equivalent.

Well, the other part of the problem is that the numbers change quite a bit depending upon where on the chart you take them from. To give an example from Intel's 22nm vs 14nm graph if you convert the percentages into normalized numbers where 0% is equal to 1 then it's not so bad to derive relative switching energy for a given delay. And the ratio of 14nm:22nm switching energy goes from 0.71 at around -25% delay to 0.55 at +55% delay. Which is to say that if TSMC's claimed performance improvements are from the low-delay side of the graph then they're quite impressive (and implies that they didn't make other sacrifices to achieve that high drive current), while if they're from the high-delay end then it's nothing special.

Anyway, that does leave the distinct possibility of TSMC's '16nm finfet' catching up to Intel's 14nm process. It'll be quite interesting to see if such actually is the case or not... or if, as usual, we don't get enough information to actually confirm one way or the other.

 

[witeken]

The Nexus 10 was released in 2012, so this is a completely unfair comparison.

True, I forgot that ARM does revisions of cores while keeping the name (A15). Even if the latest A15 consumes 1.2W and Silvermont is only 1.3x faster (total improvement of 40%), then Silvermont would still be 2x faster per watt. So I think it's still a useful comparison since it's the first time that I've seen measurements that unambiguously show Silvermont's leading performance/watt.

 

[Nothingness]

So I think it's still a useful comparison since it's the first time that I've seen measurements that unambiguously show Silvermont's leading performance/watt.

Link please?

 

[Phynaz]

TSMC already have taped out test chips on 16FF

Your point?

 

[Nothingness]

Your point?

Explained later: as per your claim ("TSMC could ship test wafers in Dec 2015"), TSMC already meet the claims they made in the email.

If you didn't get the humor underlying my answer then sorry

 

[witeken]

Link please?

Sure: http://www.realworldtech.com/forum/?threadid=133235&curpostid=133589

 

[jdubs03]

It is going to be interesting come next year when Apple releases their iPhone 6S/7. It'll be interesting to see the process behind the A9 as their are really two options in that time-frame: Samsung/GLF 14nm, and TSMC's 16 regular FinFET.

TSMC did state that they expect most customers to be running on 16FF+, so I am curious to see what Apple will decide on, as with 16FF+, the A9 could challenge Intel even more so with the more advanced process than with vanilla 16nm.

 

[Idontcare]

It is going to be interesting come next year when Apple releases their iPhone 6S/7. It'll be interesting to see the process behind the A9 as their are really two options in that time-frame: Samsung/GLF 14nm, and TSMC's 16 regular FinFET.

TSMC did state that they expect most customers to be running on 16FF+, so I am curious to see what Apple will decide on, as with 16FF+, the A9 could challenge Intel even more so with the more advanced process than with vanilla 16nm.

It will be TSMC 20nm

Don't expect high volume 16FF+ products like the iPhone to be in the market until 2016

 

[Arachnotronic]

It will be TSMC 20nm

Don't expect high volume 16FF+ products like the iPhone to be in the market until 2016

Why do you think this? Samsung is claiming 14nm in high volume by EOY 2014...

Any insight from somebody who actually can parse this sea of marketing BS would be greatly appreciated.

 

[jdubs03]

I was referring to next next-gen iPhone, so it surely wouldn't be 20nm.

 

[jpiniero]

Why do you think this? Samsung is claiming 14nm in high volume by EOY 2014...

Any insight from somebody who actually can parse this sea of marketing BS would be greatly appreciated.

IIRC, Apple signed a three year contract with TSMC and then signed a contact with Samsung for their 14 nm. Probably will use TSMC for the 6 and 6S and Samsung for the 7.

 

[shady28]

I was referring to next next-gen iPhone, so it surely wouldn't be 20nm.

The iPhone 6 with its a8 is supposed to be TSMC 20nm, not sure if that's the gen you're talking about :

http://www.phonearena.com/news/TSMC...-A8-chip-production-ahead-of-schedule_id53742

They may also be using Samsung, as there are some conflicting reports, but reports like the one above look pretty solid - they are already churning out the chips.

The whole mobile phone space has rapidly gone from 45nm (A5 / iPhone 4s) to 32nm (later versions of A5; the A6) to 28nm (A7).

I would expect to see the whole phone / ARM industry consolidate around 20nm in 2015.

I am really of the opinion that 16nm from TSMC in 2015 is not likely to show up in mass production, and the Intel 14nm will not be a magic bullet for them in the same way 22nm vs 28nm (current situation) is not.

This is the first time in a long, long time where someone will be pushing out a more advanced process node with volume before Intel gets the one-up with an even more advanced node at volume. Intel's one-up is definitely coming, but taken at face value the gap appears to have narrowed.

 

[IntelUser2000]

The problem here is that if you improve the Intel 22nm performance #'s by 40% (as claimed at Investor Meeting) to get to the 14nm numbers, you see that TSMC 16 FF and Intel 14nm are roughly equivalent.

Hmm...

I don't see this a big thing. Process "lead" is a cumulative of TTM(Time to market), transistor performance, transistor power, and density.

For years Intel has been focusing at performance, which were clock speeds. So Idrive was a big deal. But their goals are changing to lower cost, better density, and lower power. TSMC's goals are changing too. They are going for higher performance.

Naturally, each company sacrifices one aspect to get what they want: Intel with density and lower power, and TSMC with transistor performance.

Intel's 14nm is coming in products in late 2014, and TSMC's 20nm is late 2014/early 2015 as well. Actually, looking at claims from AMD/Nvidia/Qualcomm, 2015 is really early 2015. So assuming TSMC's 14nm is a year later, that puts Intel at a one year "TTM lead".

However, the 14nm from Intel is denser. It may be that its a bit less power too.

1 year earlier TTM + 0.3 generation density + 0.3 generation lower power + 0.3 generation performance equals roughly 1 generation lead, which was 24 months. I do not think its exactly 24 months, so I say 18-24 months.

Why do you think this? Samsung is claiming 14nm in high volume by EOY 2014...

Press releases claim lots of things. They are really ALL spinning, Intel, TSMC, GF, Samsung. They do not have 20nm now, and the earliest possible product is Q4 with Apple. That means Q4 2015 for 16nm/14nm at the earliest.

The thing is though since Apple is such a high volume customer, you can't really do a "pipe flush run" with them. That means if they need to delay it, then they need to delay it.

For some time, the gap between full node processes have been 24 months. Now it seems its longer, at ~27-28 months. That means any "half-node" like advancement is going to be half that, or 13-14 months. That may mean even with Q4 2014 for 20nm, it may be Q1 2016 for 14nm, at the earliest.

 

[jdubs03]

I referred to the A9, so 2015's iPhone (the next, next-gen).

I expect this years iPhone 6 with the A8 to be 20nm TSMC and less likelier 14nm Samsung. Next year I expect either 16nm FF/+ (the FF vs. + was my original point, its uncertain), or the 14nm.

Sorry for any confusion.

 

[Ajay]

Why do you think this? Samsung is claiming 14nm in high volume by EOY 2014...

Any insight from somebody who actually can parse this sea of marketing BS would be greatly appreciated.

What does "high volume" mean to TSMC, Samsung or Intel. Different things, especially with Intel. Intel's transitions to newer nodes are very fast compared to the foundry companies (in term of % of product on a new node a year after product introduction).

You'd have to suss out exactly what Samsung is claiming. According to the EET article from above

Samsung qualified its 14 nm process in February and has multiple customer chips in production in hopes of volume shipments by the end of the year.

Samsung has multiple devices in production "in hopes" of reaching volume production by the end of the year. How many wafer starts qualify as Volume production? They don't say - a pretty clear indication that they don't really know. So, it is marketing BS put out there to try and generate more interest in their latest node.

One can also glean information from semicon equipment and service providers (the 'back story' basically). Take a ASML: http://phys.org/news/2014-04-asml-lull-chip-makers.html

New orders declined to 1.07 billion euros from 1.45 billion euros. Without specifying which companies or products, ASML said chipmakers are "encountering timing uncertainties in next-generation device designs."

So there is an additional reason not to take the PR as the Gospel Truth - how can a fab be absolutely positive, when a key fab equipment supplier is seeing lower bookings due to uncertainties from the very fabs proclaiming such great news! If all were so well, they'd be looking to ramp up fast, but they are not because their yields are not stable enough to support a higher capital equipment purchases.

Finally, the kicker for even the well informed public: Khato pointed out

Anyway, that does leave the distinct possibility of TSMC's '16nm finfet' catching up to Intel's 14nm process. It'll be quite interesting to see if such actually is the case or not... or if, as usual, we don't get enough information to actually confirm one way or the other.

If you really want to go to this level of detail for the sake of developing a qualitative investment risk/reward profile - then it will take allot of research. I would think that there are professional sources of information on process development just as The Microprocessor Report does for CPUs. Secondly, you'll need to develop some professional contacts in the fab business (or maybe at college research labs) that have a better sense of what is going on in their industry (and do so while avoiding violation of SEC requirements for disclosing insider information).

This is a task that could take years to perfect. So, it comes down to where you really want to spend your energies. I would think that most, if not all, high tech industries weave a tangled web where finding actionable intelligence on future products is difficult to obtain legally. This is why most large tech companies have a "competitive analysis" group that often play in the grey (or worse) areas of the law.

TL;DR - Those who really know can't talk.