Is Intel's "Process Lead" Somewhat a Sham?

[maxP]

Intel continues to grow its process lead. I estimate them to be around 3½ years ahead. Node and transistor combined.

Please explain why Intel is contracting TSMC to fab some mobile SOCs.

[redacted]

In the future please avoid the meta commentary
-ViRGE

 

[ShintaiDK]

Please explain why Intel is contracting TSMC to fab some mobile SOCs.

Its already been answered:
http://forums.anandtech.com/showthread.php?t=2363346

 

[AtenRa]

Intel continues to grow its process lead. I estimate them to be around 3½ years ahead. Node and transistor combined.

TSMC already started production of 20nm in Q1 2014 which is equal and or better (depending of the characteristics) than Intel's 22nm. Intel started production of its 14nm process in Q1 2014 as well.
So in Q1 2014 Intel is one process ahead, now next Year TSMC will start 16nm FinFets closing the gap to half a process against Intel in 2015.

Your estimations are way wrong and doesn't meet reality.

 

[Abwx]

Please explain why Intel is contracting TSMC to fab some mobile SOCs.
We all know how biased you are by now.

They did so at GF IIRC , likely to have access to their competitor s process electrical caracteristics modeling as such a move is otherwise counter productive given their plants not being fully used currently.

 

[witeken]

Serious question for debate. With TSMC claiming that its 16nm FinFET+ will have similar performance to Intel's 14nm transistors, and with Samsung claiming 14nm high volume production this year, just how much of a process lead does Intel actually have? Why does Intel keep claiming that it's *extending* its lead here?

Seems to me that there is one but that the gap is shrinking...at least if these PRs from TSMC/GloFo are to be believed (and that's the real debate here...whether they are to be believed).

Discuss.

Wait... you (and others at SA) have written multiple articles about this topic. Here some links: 1, 2, 3, 4.

Anyway, this picture shows Intel's expanding lead:

The lines show TSMC's corresponding node. At 90nm, Intel had a lead of about 1 year. At 45/40nm, Intel had a lead of about 1,5 years. At 32/28nm and 22/20nm, Intel had a lead of 2 years. Intel's 14nm node, however, will not correspond to the competition's 20nm FinFET node ("14/16nm"), but rather to their 10nm node. So because 20nm will be here for over 3 years (50% longer), Intel's lead will increase to a staggering 3+ years.

Don't let yourself be fooled by node names or unfounded claims of equal performance (1st generation FinFET vs. 2nd generation Tri-Gate).

 

[witeken]

Intel's process lead is most certainly not a sham, but it is now as big as it's ever likely to be in foreseeable future. They have FinFETs, which are a major discontinuity, out now, and the competitors don't. That is an undisputed win by knockout. Once TSMC and Samsung have FinFET, then whose fins are better or smaller or faster or cheaper will be a win on points.
So it's unlikely that Intel will in the future have a process lead that will give it some advantage that it doesn't already have. So whatever you though the process lead was going to do for Intel, if it hasn't done it for them by now, it probably won't later.

FinFETs are nice, but the technologies that Intel will introduce 4-5 years ahead of TSMC are only going to give Intel an even more substantial advantage. What if Intel introduces III-V semiconductors with 5-10x lower power consumption, 5 years ahead of TSMC?

 

[Hans de Vries]

On June the 10th there will be combined presentation of IBM, Samsung,
ST, GF and UMC at VLSI-2014.



A 10nm Platform Technology for Low Power and High Performance
Application Featuring FINFET Devices with Multi Workfunction
Gate Stack on Bulk and SOI
,
K.I. Seo*, B. Haran, D. Gupta, D. Guo, T.Standaert, R. Xie
***, H. Shang, E. Alptekin, D.- I. Bae*, G. Bae*, C. Boye,
H. Cai***, D. Chanemougame**, R. Chao, J. Cho***, B. Hamieh**
, J.G. Hong*, T. Hook, L. Jang***, J. Jung*, R. Jung, D. Lee*
, B. Lherron**, R. K ambhampati***, B. Kim*, H. Kim***, K. Kim*
, T.S. Kim*, S.-B. Ko, F.L. Lie, D. Liu, H. Mallela, E.Mclellan,
S. Mehta, P. Montanini**, M. Mottura**, J. Nam, S. Nam***,
F. Nelson, I. Ok, C. Park***, Y.Park*, A. Paul***, C. Prindle***
, R. Ramachandran, M. Sankarapandian, V. Sardesai, A. Scholze,
S.-C.Seo, J. Shearer, R. Southwick, S. Stieg, J. Strane, X. Sun,
M.G. Sung***, S. Surisetty, G. Tsutsui, N.Tripathi***, R. Vega,
C. Waskiewicz, M. Weybright, C.-C. Yeh, H. Bu, S. Burns,
D. Canaperi, M. Celik**, M.Colburn, H. Jagannathan,
S. Kanakasabaphthy, W. Kleemeier**, L. Liebman, D. Mcherron,
P. Oldiges, V.Paruchuri, T. Spooner, J. Stathis, R. Divakaruni,
T. Gow, J. Iacoponi***, J. Jenq^, R. Sampson**, M. Khare,

IBM Microelectronics, *Samsung Electronics,**STMicroelectronics,
***GLOBALFOUNDRIES, ^UMC

A 10nm logic platform technology is presented for low power and high
performance application with the tightest contacted poly pitch (CPP)
of 64nm and metallization pitch of 48nm ever reported in the FinFET
technology on both bulk and SOI substrate. A 0.053μm2 SRAM bit-cell
is reported with a corresponding Static Noise Margin (SNM) of 140mV
at 0.75V. Intensive multi-patterning technology and various self-
aligned processes have been developed with 193i lithography to over-
come optical patterning limit. Multi-work function (WF) gate stack
has been enabled to provide Vt tunability without the variability
degradation induced by channel dopants.

 

[Arachnotronic]

Wait... you (and others at SA) have written multiple articles about this topic. Here some links: 1, 2, 3, 4.

Anyway, this picture shows Intel's expanding lead:

The lines show TSMC's corresponding node. At 90nm, Intel had a lead of about 1 year. At 45/40nm, Intel had a lead of about 1,5 years. At 32/28nm and 22/20nm, Intel had a lead of 2 years. Intel's 14nm node, however, will not correspond to the competition's 20nm FinFET node ("14/16nm"), but rather to their 10nm node. So because 20nm will be here for over 3 years (50% longer), Intel's lead will increase to a staggering 3+ years.

Don't let yourself be fooled by node names or unfounded claims of equal performance (1st generation FinFET vs. 2nd generation Tri-Gate).

I am quite aware of Intel's claims and now of those of Intel's competition.

At this point, I'm not really sure who to believe. Intel has yet to release the details of its 14nm process, but TSMC and Samsung have (to some extent).

 

[witeken]

Much lower transistor cost, 67% lower power, 40% higher peformance (take those 2 claims with a pinch of salt until we see independent benchmarks, though), continuation of Dennard scaling. Also see this informative article: Intel’s 14nm milkshake: It’s better than yours.

14nm seems like an excellent node, vastly superior compared to 20nm, 20nm FinFET and probably competitive/similar to the competition's 10nm. So I wouldn't worry about Intel process lead. It certainly isn't shrinking, that's for sure.

Edit: And I'd better listen to Intel's claims. As we've seen with TSMC's rebuttal, it doesn't really contain any facts.

 

[azazel1024]

Here is the thing. None of the other foundries have 20nm transisters in shipping CPU/APU/SoC products to consumers yet. The best estimate is sometime in 2H2014 and possibly 3Q2014 for ANY 20nm products to consumers.

Samsung hitting 14nm this year...probably. For their NAND FLASH A lot of guys are pretty far down for flash. The requirements on that stuff isn't nearly as stringent as that for CPUs/GPUs/RAM.

The best estimate is that anything smaller than 20nm, like TSMCs hybrid 16/20nm FinFET design (it isn't true 16nm) probably won't see shipping consumer products in 2015, probably 2016.

What can be produced in a lab or in small scale prototype product is vastly different from actually having the lithography up and running in your factory and producing volume with sufficiently low losses. Intel has had 14nm up and running for well over a year for lab, prototype and engineering production. Its been delayed a few months because they are tweaking it to get yields high enough to get the kind of margins Intel wants on them.

TSMC/GF have had 20nm in the same state for several months now...but they still aren't looking to have appropriate yields until the second half of this year...after Intel is almost certain to have shipping 14nm products to consumers.

Sammy/TSMC/GF aren't likely to have shipping sub-20nm product for at LEAST 2 years after they hit 20nm. It could be 3 years or more possibly. They don't turn around all of the expensive lithography machines they just bought at 20nm and go through another multibillion dollar purchasing spree to get the next node out the door a matter of months after they just made 20nm commercially viable.

Frankly I don't care who has the best node, so long as everyone is advancing technology. That said, Intel certainly seems to have the most advanced process currently and they have a minimum of a 3-6 month lead assuming you want to even charitably call everyone elses 20nm node as good as Intels 14nm (protip, it won't be. I'd bet large loons on that). If you call 20nm non-FinFET as good as Intel's 22nm FinFET (it might be, but possibly still not), then everyone else is roughly 3 years behind Intel at this point and they don't seem to be catching up (or if they are, not by much).

 

[teejee]

Sammy/TSMC/GF aren't likely to have shipping sub-20nm product for at LEAST 2 years after they hit 20nm. It could be 3 years or more possibly. They don't turn around all of the expensive lithography machines they just bought at 20nm and go through another multibillion dollar purchasing spree to get the next node out the door a matter of months after they just made 20nm commercially viable.
.

Of course they won't replace 20nm equipment with 14nm after a few months of production, they have different factories and/or different production lines. The replace 28nm or older equipment with 14nm.
Your post is based on wrong assumptions.

 

[azazel1024]

Of course they won't replace 20nm equipment with 14nm after a few months of production, they have different factories and/or different production lines. The replace 28nm or older equipment with 14nm.
Your post is based on wrong assumptions.

Half my point is more that with all of the work on 20nm, I don't see them suddenly being able to jump from taking 3+ years to get 20nm out the door to suddenly being able to jump in to 14/16nm products that quickly.

Anything smaller than 20nm is likely to lag a minimum of 12 months and probably closer to 36 months after they finally manage to get 20nm in shipping products.

 

[AtenRa]

Half my point is more that with all of the work on 20nm, I don't see them suddenly being able to jump from taking 3+ years to get 20nm out the door to suddenly being able to jump in to 14/16nm products that quickly.

Anything smaller than 20nm is likely to lag a minimum of 12 months and probably closer to 36 months after they finally manage to get 20nm in shipping products.

GloFo/Samsung and TSMC’s 14/16nm FinFets are Half-Nodes of 20nm, they use almost the same machinery and in fact they use the same BEOL on both of them. Resources and time to make the process is less than make a new Full-Node process like 20nm over 28nm.

Also, they will use both processes simultaneously so they can start volume production of the FinFets one year after 20nm.

 

[Nothingness]

Seems to me that there is one but that the gap is shrinking...at least if these PRs from TSMC/GloFo are to be believed (and that's the real debate here...whether they are to be believed).

And that's a question that can't be answered at the moment. Believing this marketing presentation is no better than believing Intel marketing. Even Intel has yet to prove 14nm performance, all we have now are their slide decks and I've seen enough errors, approximations and lies in them that I don't believe them as I used to.

So let's wait, but as a customer, I would be happy if the existing gap was shrinking.

 

[Khato]

Excellent post as usual IDC,
I will only add that because of Intel's intentions to enter the mobile market that GloFo/Samsung/TSMC are now investing more and adjust their processes to match Intel's.
They also have to be more competitive now because Intel has started producing not only for itself but for others too. So they know very well that if they slip more behind they will soon loose customers to Intel.

I will also add that SamSung/GloFo 14nm FinFet and TSMCs 16nm FinFet are closer to Intel's 14nm in electrical/performance characteristics than density. From the little available data we have, it seams to me that Intel will have better density.

The first half of the above is all too often overlooked and is spot on. Look back almost 3 years - when did TSMC first announce their finfet plans? Less than 2 weeks after Intel's 22nm finfet announcement - http://www.itproportal.com/2011/05/16/tsmc-pushes-finfet-tech-back-14nm-process-size/ Then there's the most recent example of TSMC's '16nm FF+' creation coming hot on the heels of Intel's claim that they'd have a marked density advantage over TSMC's '16nm FF' process. It used to be that AMD/GlobalFoundries was the one with joke roadmaps, but now TSMC seems to be joining those ranks for the exact same reason - they actually have to compete against Intel. And how do you compete/not lose customers when you're behind? You make 'me-too' PR announcements to counter the competition. And it actually works for awhile because of the length of design cycles - customers are designing for and locked into a process long before there's any indication that it's not going to make the promised schedule.

As for the second point, that actually touches on the reason why it's rather obvious that TSMC is just posturing - what data on Intel's 14nm process are you referencing again? Because last I checked the only data points that Intel has released are a series of charts that leave a pretty large margin of error and an example of early Broadwell silicon delivering the same performance as Haswell at 72% the power consumption. So how precisely can TSMC claim that they're on equal footing when they don't have a clue on the actual specs of Intel's 14nm process?

 

[AtenRa]

As for the second point, that actually touches on the reason why it's rather obvious that TSMC is just posturing - what data on Intel's 14nm process are you referencing again? Because last I checked the only data points that Intel has released are a series of charts that leave a pretty large margin of error and an example of early Broadwell silicon delivering the same performance as Haswell at 72% the power consumption. So how precisely can TSMC claim that they're on equal footing when they don't have a clue on the actual specs of Intel's 14nm process?

Im not referring to the Intel's PR slide, the one TSMC had to respond with another PR slide. Im referring mostly to the Metal Stack of the 14/16nm FinFets as being larger than Intels 14nm Metal Stack simple because GloFo/Samsung and TSMC will use the BEOL of 20nm.
So even if all three will manage to have the same Transistor size(Gate Length, pitch etc) Intel will have an advantage with smaller Metal Stack and thus higher density.

 

[Sho'Nuff]

There is a lot more to Intel's process lead then simply volume production at 14nm. They have numerous technologies that Samsung does not. All 14nm transistors are not the same. So regardless of whether Samsung can produce at that size, I would say that Intel still has a substantial lead on them simply because of their technological advances in the IC/CPU architecture space.

 

[AtenRa]

@ Sho'Nuff

Shogun of Harlem :thumbsup::thumbsup::thumbsup::thumbsup::thumbsup::thumbsup:

Shonuff rulzzzzzzz

 

[Hans de Vries]

Anyway, this picture shows Intel's expanding lead:

Wow, don't show that marketing piece to Morris Chang. He will get a heart attack from anger

What Morris should have done right away is showing that the infamous
slide claims that Intel's density increases by a factor 3 going from 22nm
to 14nm. (~3 = 1.9 * 1/(1-0.35) ), with 1.9 = TSMC's 28nm --> 20nm.

A lot more realistic scaling of 2.1 was shown last month by Mark Bohr in
Shanghai, on page 16

So the CEO's number is 3 while the chief technical guy's number is 2.1

Can you guess which number I take more seriously?

 

[SlimFan]

So the CEO's number is 3 while the chief technical guy's number is 2.1

Can you guess which number I take more seriously?

One is "area scaling" and one is "transistor scaling." They can both be accurate where one represents a product level answer, while the other one is a specific feature of that process.

Area scaling is the one that would matter more to cost/products. You can see Intel is showing that 22nm wasn't ahead at an area level, while it might have been ahead on transistor pitch. It would be interesting to revisit your the "ARM vs IA" CPU size comparisons in this context.

 

[Hans de Vries]

One is "area scaling" and one is "transistor scaling." They can both be accurate where one represents a product level answer, while the other one is a specific feature of that process.

Area scaling is the one that would matter more to cost/products. You can see Intel is showing that 22nm wasn't ahead at an area level, while it might have been ahead on transistor pitch. It would be interesting to revisit your the "ARM vs IA" CPU size comparisons in this context.

It's not "transistor scaling". It says "mm2/transistor" scaling.

If you include the less scaling area's (like the I/O) in the "area-scaling", then
the "mm2/transistor" scaling becomes well over 3 and not less.

 

[Khato]

Im not referring to the Intel's PR slide, the one TSMC had to respond with another PR slide. Im referring mostly to the Metal Stack of the 14/16nm FinFets as being larger than Intels 14nm Metal Stack simple because GloFo/Samsung and TSMC will use the BEOL of 20nm.
So even if all three will manage to have the same Transistor size(Gate Length, pitch etc) Intel will have an advantage with smaller Metal Stack and thus higher density.

Which is true, but not what you said

I will also add that SamSung/GloFo 14nm FinFet and TSMCs 16nm FinFet are closer to Intel's 14nm in electrical/performance characteristics than density. From the little available data we have, it seams to me that Intel will have better density.

I believe TSMC is the only one who has given any information regarding the electrical/performance characteristics of their '16nm finfet' process. All we have from Intel on the subject are the rough charts comparing to 22nm, which could either put them further ahead again in that area than they are with respect to density or not. TSMC's published characteristics on their '16nm finfet' imply that it will be slightly superior to Intel's 22nm process... which given that Intel's early Broadwell demo had it using 72% the power of Haswell at same performance implies that TSMC's '16nm finfet' isn't any closer to Intel's 14nm in electrical/performance characteristics than it is in density.

 

[Khato]

What Morris should have done right away is showing that the infamous
slide claims that Intel's density increases by a factor 3 going from 22nm
to 14nm. (~3 = 1.9 * 1/(1-0.35) ), with 1.9 = TSMC's 28nm --> 20nm.

Two questions. First, what metric are you using for the 1.9x factor for TSMC from 28nm to 20nm? Second, doesn't your equation assume that density is equal between TSMC's 28nm and Intel's 22nm?

 

[witeken]

Wow, don't show that marketing piece to Morris Chang. He will get a heart attack from anger

What Morris should have done right away is showing that the infamous
slide claims that Intel's density increases by a factor 3 going from 22nm
to 14nm. (~3 = 1.9 * 1/(1-0.35) ), with 1.9 = TSMC's 28nm --> 20nm.

A lot more realistic scaling of 2.1 was shown last month by Mark Bohr in
Shanghai, on page 16

So the CEO's number is 3 while the chief technical guy's number is 2.1

Can you guess which number I take more seriously?

Interesting. What I'm now wondering is why the person came to the conclusion in this article that Intel's slide is accurate: TSMC's Rebuttal Of Intel's Scaling Advantage Is Just Qualitative, Not Quantitative.

What I'm especially wondering is how you came to the conclusion that Brian Krzanich in his (in)famous slide stated a 3x density improvement. According to the article linked above, 14nm will offer a 2.26x density improvement (0.585/0.259), which is no where near your 3x claim.

What's interesting is that, on top of that fact that the article claims that Intel's slide is accurate, another indication of the correctness is that Intel's slide claims a 1.7x area scaling of 32->22nm (1/0.585). This is spot on if we look at the data that is available: Sandy Bridge has 1.16B layout transistors and an area of 216mm², while Haswell has 1.6B layout transistor in 177mm², resulting in a scaling of 1.68.

TL;DR: Intel's slide still seems to be absolutely correct, with 14nm promising 2.25x scaling.

 

[TuxDave]

What Morris should have done right away is showing that the infamous slide claims that Intel's density increases by a factor 3 going from 22nm to 14nm. (~3 = 1.9 * 1/(1-0.35) ), with 1.9 = TSMC's 28nm --> 20nm*

* Assumptions made:
(1) INTC @ 22/20nm = TSMC @ 32/28nm
(2) TSMC @ 22/20nm = TSMC @ 14/16nm

Unless you have data outside the "marketing graph", those are questionable assumptions since it's a log-graph with no labels on the Y-axis. The dots sort of look lined up but who knows if it's artistic interpretation and where the major axis breakpoints are.