So why 450 mm and not say, 1000 mm?
It goes right back to the same fundamentals that are the cause of node shrinking too.
The industry transitions wafer sizes about every 10 yrs for pretty much the same economic reasons that motivates it to transition process nodes every 2-3 yrs.
Why do successive nodes tend to target a 70.7% linear shrink and a 50% areal shrink? And why every 2yrs?
Why not make the shrink targets and timeline more aggressive? Why not a 50% linear shrink, 25% areal shrink, and do it every 6 months?
Short Answer: Money
Long Answer: The
Project Management Triangle
^ you can prioritize 2 of the 3, but no more than two.
Scope (shrink targets) and schedule (cadence) are constrained by cost (R&D budget).
The industry settled on a fairly standardized node scaling target (70.7% linear, 50% areal) as well as a common cadence (2yrs) not because of R&D cost goals but because of competitive pressures which drove R&D costs to be such that a 2yr/50% areal node shrink was the optimal business strategy.
If you didn't fund your R&D efforts as needed to enable the R&D team to roll out a new node every 2yrs which had a 50% areal shrink factor then your products on the marketplace would be at a competitive disadvantage...so you funded appropriately (if you had the means to do so).
It was this same competitive motivation that resulted in the foundries having half-nodes. Baby-stepping in one year increments. You probably noticed that as soon as TSMC was no longer competing with the other foundries (post 55nm) in terms of node release timeline the half-node option completely disappeared. TSMC doesn't need it to compete with other foundries, so they don't spend money developing it...and the other foundries can't afford to fund the development of half-nodes anymore as they can barely afford to develop the full nodes on a somewhat competitive timeline (and even that is questionable).
Companies that did not have the means started to slip, their node cadence became 2.5yrs, or 3yrs, or the areal shink factor was something less than 50%, etc.
All right, so what does this have to do with increasing wafer size? The very concept of increasing the wafer size is a product of the very concept of shrinking the node - it is about cost reduction and remaining competitive.
And it is bound by the same constraints - scope (targeted wafer size) and schedule (timeline) are constrained by cost (R&D budget).
Traditionally the scope of wafer-size increases was on the order of 1.25x-1.78x, but the schedule (cadence of wafer size increases) was much shorter then (~2-3 yrs) versus what it is now (~10-12yrs).
http://upload.wikimedia.org/wikipedia/commons/b/b9/Silicon_wafer_diameter_progression.jpg
Over the past 2 decades the industry has standardized on the scope (this was your original question) as being 2.25x increase in wafer surface area. A 75mm wafer had 2.25x the surface area of a 50mm wafer, 150mm had 2.25x the area of a 100mm wafer, 300mm has 2.25x the area of a 200mm wafer, and when it goes into production a 450mm wafer will have 2.25x the area of a 300mm wafer.
2.25x area increase (the scope of the wafer increase project) on a 10-12yr rollout schedule is basically the optimum use of the industry's R&D money when it comes to creating the opportunity to reduce production costs by ~25-30%.
If they tried to go from 300mm to 1000mm then the timeline would have to be drastically relaxed (goal might be to put it into production in 2030) or the R&D investment would have to be significantly higher (which would then reduce the net cost benefit of the increased wafer size).
Same reasoning behind why Intel doesn't just skip 14nm and 10nm and go straight from 22nm to 7nm. They could if they wanted, but it would cost a bundle to make it happen and then all the economic motivation for the creating the shrink in the first place goes out the window.
)
Facebook
Twitter