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Is 7nm the practical limit?

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moinmoin

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Here's a new article posted on 5nm and potential 3nm. Seems 5 will be done, though 3nm can probably be done too, though the big question is how many customers will there be for 3nm if costs to develop a chip are 500m -1.5b

https://semiengineering.com/5nm-vs-3nm/
Cost is the biggest issue indeed. That's essentially why a pure play foundry like TSMC is about to surpass self proclaimed "process leader" Intel: The biggest push for ever smaller nodes comes from mobile phone manufacturer, and the mobile market is big enough to ensure enough customer demand = funding for new nodes. So far anyway. It looks like the mobile phone market is plateauing right now so the high costs for 3nm will be prohibitive even there, ensuring the current cadence likely stops at that point.

The article notes the strong reliance on FinFET so far, that the fin width of 3nm is bordering the physical limit. Other approaches are required, but prohibitive cost as well as the lack of bleeding edge foundries remaining (only TSMC, Samsung and Intel) may lead to insufficient R&D being spent in that particular field.
 

soresu

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Dec 19, 2014
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The thing with breakthroughs are that they're unpredictable. Trying to do so, is often an exercise in frustration. Witness fusion energy.
The problem with fusion energy is that the lions share of capital investment in research has been in Tokamak style magnetic confinement techniques, which I have seen likened to using a sledgehammer instead of a scalpel to solve the problem.
Many other more innovative techniques have been displayed in more recent years, but they have not been given the necessary capital to investigate to nearly the degree to which Tokamaks have been (see ITER, cry at the billions going down that money drain).

As for 3nm, there is a Gate All Around device called a Nano Sheet that will replace the aging FinFET device at that node, possibly followed by a revision of this new device called a Fork Sheet at the 2 or 1.5nm process.

The first iteration will offer higher performance than FinFET at the expense of density, while the second Fork Sheet will supposedly surpass FinFET density scaling.
 

soresu

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Dec 19, 2014
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can also SMP things, such as Neon
NEON/MMX/SSE/AVX is vector SIMD, as opposed to scalar arithmetic - which is separate from SMP (Symmetric multiprocessing), though they can be, and are done at the same time on most modern CPU systems.

SMP basically just means multi threading/multi process over multiple CPU's or cores.
 

soresu

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Dec 19, 2014
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Just remember how long it took get OLEDs to work to large displays
They don't put it about, but blue OLED's still have relatively short lifetimes compared to red and greeen OLED's - which is exascerbated by HDR display tech pumping up the luminance to more than 1000 nits.
 

soresu

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Dec 19, 2014
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Going past the new GAA Nano Sheet device derivatives, they may have to shift the logic paradigm entirely from standard CMOS electronics to something spintronic, like Intel's MESO idea, or Spin Wave Majority Gate (which can actually operate at several frequencies at once, possibly increasing compute density within single devices).

For logic alone, spintronic paths seem like the prevailing choice going forward - it's potentially far less thermally constricting, and therefore highly appropriate for vertical scaling (layers/stacking), which will be important as they reach physical scaling limits for area alone.
 

Xpage

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Jun 22, 2005
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www.riseofkingdoms.com
The problem with fusion energy is that the lions share of capital investment in research has been in Tokamak style magnetic confinement techniques, which I have seen likened to using a sledgehammer instead of a scalpel to solve the problem.
Many other more innovative techniques have been displayed in more recent years, but they have not been given the necessary capital to investigate to nearly the degree to which Tokamaks have been (see ITER, cry at the billions going down that money drain).

As for 3nm, there is a Gate All Around device called a Nano Sheet that will replace the aging FinFET device at that node, possibly followed by a revision of this new device called a Fork Sheet at the 2 or 1.5nm process.

The first iteration will offer higher performance than FinFET at the expense of density, while the second Fork Sheet will supposedly surpass FinFET density scaling.

Cool, haven't herad about fork sheets yet. I do think they'll get GAA to work, but not sure how many people will use it. I can see a 3nm++++ process, which are only minor tweeks for CPUs. So if you like Intel's architecture lasting years, get ready for the future. Then maybe years down the line they'll release a 2nm or 1.5nm and sit on that for a decade until one company decides they'll go to 1nm. I think these last few nodes will all be about what customer wants it and then how many years it takes to get it paid off so prices drop to get more companies to use it to further drop costs, to bring in more people so they can get R&D to try to find a new process.

I do think a major change in CPU logic or transistor architecture will be needed at some point
 

soresu

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Dec 19, 2014
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but not sure how many people will use it
The benefit of ARM's IP licensing model is that they have already done a large amount of the design work in creating synthesizable cores that are more or less modular from a chip level design POV.

Working on just cores lets them focus on a much smaller area of silicon for each process.
As opposed to AMD, Intel or nVidia that have to design the whole chip in one go - even if they have the basic uArch recipe to start with, it's still a lot to cover as the nodes get smaller and more expensive to develop for.
 

soresu

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Dec 19, 2014
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This is a tricky área to discuss due to different definitions and all that but if we simply follow the vendor denomination TSMC already taped out its 5nm process.
AMD previously had Zen 4 marked down for 5nm somewhere I'm sure I've seen, and now the E3 slides showing Zen 4 are just blank for the process node, which leads me to think they are considering skipping 5nm for the greater benefits of the 3nm jump, probably meaning we will get a Ryzen 5000 series which is basically a new stepping of Zen 3 with a little extra frequency scaling (Zen 3+ if you will....).

Edit: I can't find that Zen 4/5nm slide, must have seen it on a forum instead, DOH!!!

The scaling benefits from 7nm+ to 5nm are minimal, its unlikely to be worth AMD's investment in money and time when 3nm won't take that much longer, its early PDK is already circulating since mid May.

Also another name for Nano Sheet is MBCFET (Multi Bridge Channel Field Effect Transistor), its still a GAA type device though.
 
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soresu

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Dec 19, 2014
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Edit: Sorry posted in the wrong thread (where is the delete button almighty admin?!).
 
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moinmoin

Golden Member
Jun 1, 2017
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The benefit of ARM's IP licensing model is that they have already done a large amount of the design work in creating synthesizable cores that are more or less modular from a chip level design POV.

Working on just cores lets them focus on a much smaller area of silicon for each process.
As opposed to AMD, Intel or nVidia that have to design the whole chip in one go - even if they have the basic uArch recipe to start with, it's still a lot to cover as the nodes get smaller and more expensive to develop for.
I'd say at least AMD is an exception in that group, they have been working on modularizing all their IPs since taking over ATi. Their GPUs have been modularized since then and have seen minor updates to each module individually as opposed to general overall updates (Navi will be the first in ages). They started modularizing their CPUs with the Construction/Cat cores. These efforts enables their semi-custom business to begin with. And I'd say it's also responsible for AMD being able to make these big changes in Zen package architecture with relatively little turnaround time, while jumping process nodes.

AMD previously had Zen 4 marked down for 5nm somewhere I'm sure I've seen, and now the E3 slides showing Zen 4 are just blank for the process node, which leads me to think they are considering skipping 5nm for the greater benefits of the 3nm jump, probably meaning we will get a Ryzen 5000 series which is basically a new stepping of Zen 3 with a little extra frequency scaling (Zen 3+ if you will....).

Edit: I can't find that Zen 4/5nm slide, must have seen it on a forum instead, DOH!!!

The scaling benefits from 7nm+ to 5nm are minimal, its unlikely to be worth AMD's investment in money and time when 3nm won't take that much longer, its early PDK is already circulating since mid May.

Also another name for Nano Sheet is MBCFET (Multi Bridge Channel Field Effect Transistor), its still a GAA type device though.
AMD's plan so far seem to be to start with non-EUV at TSMC (Zen 2 using 7nm), then jump onto EUV (Zen 3 using 7nm+). After going for EUV it makes no sense to back out again, so the next EUV based node would be the natural upgrade path.

At TSMC the update to 7nm is 6nm, the update to 7nm+ is 5nm. I wouldn't be so sure 3nm won't take much longer than 5nm. In any case the jump from 7nm+ to 5nm won't be as expensive as 7nm to 7nm+ since 5nm largely builds upon the specs and tools of 7nm+. 3nm again will be a relatively clean break.

Personally I expect AMD will try to hold up their close to yearly node launch cadence. For this it's better to follow TSMC's pattern paved by other customers instead jumping to bleeding edge nodes that may still end up being delayed.
 

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