Did anyone catch this?
<< The Hammer, which is an eighth-generation processor, is 103 square mm, versus our seventh generation, which is 80 square mm. [There are] 67 million transistors in the Hammer?67 million transistors in 130-nanometer technology. It?s extraordinary. >>
I remember AMD having disclosed the die-size of the Hammer before, but not the transistor count (only a vague 100 million statement for Sledgehammer which I suppose they meant the 1MB L2 cache version.)
With 67 million transistors it should be pretty given that Clawhammer will contain 512KB of L2 cache, right? And that would possibly suggest an inclusive L2 cache since the same cache will be used in the 1MB L2 version of Sledgehammer. What do you guys think?