http://www.xbitlabs.com/news/story.html?id=1019274490
The major thing is that Prescott will be not only a 0.09micron version of Northwood core, but will boast a number of enhancements telling positively on its performance. The first major difference will make the larger L1 cache for data. Different source report that it will get two times or four times bigger compared with L1 cache for data by Willamette and Northwood, i.e. it will be equal to 16KB or 32KB. Instruction Trace Cache may also be increased (see the details about Pentium 4 architecture in our articles on Willamette and Northwood). However, there is no other info on that as we don?t actually know its exact size by Willamette and Northwood.
The next pretty predictable innovation is the increase in L2 cache size. Here everything is more or less certain: it will be equal to 1MB (twice as big as L2 cache by Northwood, and four times as big as by Willamette).
Prescott is also reported to support an enhanced HyperThreading technology (see this news story), which allows working with one CPU, as if there were two or more of them in a system. As you know, this technology is already implemented in Xeon MP (Prestonia) CPUs.
One of the most interesting innovations in the upcoming Prescott processor will be Yamhill technology (similar to x86-64, 64bit 86x instructions). However, Intel hasn?t yet made up its mind about adding this technology to Pentium 4. Once they decide to add it, the die size of the Pentium 4 processor is expected to grow only 2% bigger. In fact, this is very small sacrifice for a promising technology trend (which can actually kill Itanium).
How would an x86-64 capable Pentium 4 kill the IA-64 program? IA-64 has been aimed at the niche high-end server market since the beginning, whereas an x86-64 Pentium 4 would seemingly be positioned in the low-end server and Xeon markets.
The major thing is that Prescott will be not only a 0.09micron version of Northwood core, but will boast a number of enhancements telling positively on its performance. The first major difference will make the larger L1 cache for data. Different source report that it will get two times or four times bigger compared with L1 cache for data by Willamette and Northwood, i.e. it will be equal to 16KB or 32KB. Instruction Trace Cache may also be increased (see the details about Pentium 4 architecture in our articles on Willamette and Northwood). However, there is no other info on that as we don?t actually know its exact size by Willamette and Northwood.
The next pretty predictable innovation is the increase in L2 cache size. Here everything is more or less certain: it will be equal to 1MB (twice as big as L2 cache by Northwood, and four times as big as by Willamette).
Prescott is also reported to support an enhanced HyperThreading technology (see this news story), which allows working with one CPU, as if there were two or more of them in a system. As you know, this technology is already implemented in Xeon MP (Prestonia) CPUs.
One of the most interesting innovations in the upcoming Prescott processor will be Yamhill technology (similar to x86-64, 64bit 86x instructions). However, Intel hasn?t yet made up its mind about adding this technology to Pentium 4. Once they decide to add it, the die size of the Pentium 4 processor is expected to grow only 2% bigger. In fact, this is very small sacrifice for a promising technology trend (which can actually kill Itanium).
How would an x86-64 capable Pentium 4 kill the IA-64 program? IA-64 has been aimed at the niche high-end server market since the beginning, whereas an x86-64 Pentium 4 would seemingly be positioned in the low-end server and Xeon markets.
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