- Oct 14, 1999
- 11,999
- 307
- 126
Intel to blow BBULs
Posted 10/10/2001 - 12:36AM, by Hannibal
The big processor news of the day, other than the Athlon XP launch, was Intel's announcement of a new packaging technology called bumpless buildup layer (BBUL). For a good technical write-up, check the EET. For a more general overview, I'll try to explain briefly the new tech as best I can, but I admit that I'm not really a packaging expert. (Perhaps one of the board layout and packaging types who frequent the OpenForum might care to contribute in the discussion link ;-) Anyway, here goes. Intel currently uses a layer of solder beads (or "C4 bumps"), which are connected to the CPU die, to transmit I/O signals from the silicon CPU die to the CPU package's pins. Signals going from the system into the CPU travel through the package's pins and up through an internal package layer ("Package core with vias" in the pic below), where they're routed to the correct bump. The bumps then transmit these signals into the CPU die itself. Output signals follow the same path, but in reverse. Note that in Intel's current BGA packaging scheme, these pins are replaced by balls. The following image, from this Intel document, illustrates the point.
In the new packaging scheme, Intel has done away with the top layer and the bumps by actually embedding the silicon CPU die into the package substrate itself. In effect, the CPU sits inside what amounts to a copper via. Check it:
This new scheme has whole host of advantages, but I'll run down only a few here. First, the package is thinner, meaning BBUL devices would be ideal for mobile applications. Next, shortening the distance between the pins and the CPU die enables higher frequencies by reducing pin inductance and allowing capacitors to be placed closer to the die for less noisy and more efficient signal and power delivery. This means that chips made using BBUL can run faster and support a higher number of I/O pins (which we'll need as transistor counts rise). BBUL will also make it easier to integrate multiple chips (nForce + CPU + RAM?) into one thin package so that you can do cool system-in-a-package type applications. Anyway, you can find more details on the advantages here and on the potential applications in the EET piece. Oh, and one last thing: file this one in the "four to five years away" category.
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Otherwise the heat spreader will not be necessary. Looks like AMD now has two technologies to absorb, mPGA and BBUL.
Edit: Forgot to mention that Intel's document makes a statement about this technology making it possible to integrate multiple cores (read = SMT and/or L3 cache?) into the socketed design.
Posted 10/10/2001 - 12:36AM, by Hannibal
The big processor news of the day, other than the Athlon XP launch, was Intel's announcement of a new packaging technology called bumpless buildup layer (BBUL). For a good technical write-up, check the EET. For a more general overview, I'll try to explain briefly the new tech as best I can, but I admit that I'm not really a packaging expert. (Perhaps one of the board layout and packaging types who frequent the OpenForum might care to contribute in the discussion link ;-) Anyway, here goes. Intel currently uses a layer of solder beads (or "C4 bumps"), which are connected to the CPU die, to transmit I/O signals from the silicon CPU die to the CPU package's pins. Signals going from the system into the CPU travel through the package's pins and up through an internal package layer ("Package core with vias" in the pic below), where they're routed to the correct bump. The bumps then transmit these signals into the CPU die itself. Output signals follow the same path, but in reverse. Note that in Intel's current BGA packaging scheme, these pins are replaced by balls. The following image, from this Intel document, illustrates the point.
In the new packaging scheme, Intel has done away with the top layer and the bumps by actually embedding the silicon CPU die into the package substrate itself. In effect, the CPU sits inside what amounts to a copper via. Check it:
This new scheme has whole host of advantages, but I'll run down only a few here. First, the package is thinner, meaning BBUL devices would be ideal for mobile applications. Next, shortening the distance between the pins and the CPU die enables higher frequencies by reducing pin inductance and allowing capacitors to be placed closer to the die for less noisy and more efficient signal and power delivery. This means that chips made using BBUL can run faster and support a higher number of I/O pins (which we'll need as transistor counts rise). BBUL will also make it easier to integrate multiple chips (nForce + CPU + RAM?) into one thin package so that you can do cool system-in-a-package type applications. Anyway, you can find more details on the advantages here and on the potential applications in the EET piece. Oh, and one last thing: file this one in the "four to five years away" category.
*********************************************************************************************
Otherwise the heat spreader will not be necessary. Looks like AMD now has two technologies to absorb, mPGA and BBUL.
Edit: Forgot to mention that Intel's document makes a statement about this technology making it possible to integrate multiple cores (read = SMT and/or L3 cache?) into the socketed design.
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