Intel's 90nm 6T SRAM layout.

[rimshaker]

The front story on Intel's 90nm Prescott L2 cache is a good read. I'm simply amazed at how some engineers found a way to lay out a single-cell 6-transistor SRAM in an area of only 1 um^2 in the 90nm process. The next closest competitor can 'only' lay out a 6T SRAM in 1.36 um^2. It's all in the design and a really innovative cell layout. Man, i'm dying to know what that secret cell layout looks like.....

 

[pm]

<< It's all in the design and a really innovative cell layout. >>

...and very tight design rules. Tight design rules require better processing capability by the fab. But if you can slap two poly's side-by-side closer than your competitor, then you can get a smaller size cell without having to do anything really tricky. SRAM cells are only 6T... there are only so many ways to lay 6 transistors out.

 

[rimshaker]

I guess it's just you and me on these types of topics pm... 🙁

 

[Mucman]

I've always been curious of how the actual memory storage on the chip is implemented...

Is it a D Flip Flop? So 6Ts would mean 3 gates, correct?

 

[PicPop]

^

 

[Sohcan]

A 6T SRAM cell in CMOS (unless something has changed with today's smaller lithography, and my texts are outdated) is formed by two cross-coupled inverters, as well as two access transistors. I believe D-type flip-flops are only used for registers, since the edge-triggered behavior is costly in the number of transistors.

 

[Agent004]

<< I guess it's just you and me on these types of topics pm... 🙁 >>



Well those knows enough detail about, can't really post about it. Those who doesn't know it in depth can't post anything (good, technical) about it


<----------------- the latter describes this post perfectly

🙁