Hi all.
I have a question about the performance of the on-die memory controller on the nehalem based and barcelona, shanghai, istanbul, magny cours architecture. Is the performance gap in stream, everest, sandra etc ... only due to the memory controller even after the balancing memory resources (same number of memory channels (lynnfield), frequency and memory timing) or is there something else important. The reason to ask this question is that my work is concerning about the HPC computing with the memory demanding applications (calculations of electronic structure in molecules and solids), where we see the strong correlation between the performance and the memory throughput. Is really Nehalem based systems so good for the memory demanding applications? And the reason is the excellent on-die memory controller on Intel side or AMD cannot utilize all memory resources?
I have a question about the performance of the on-die memory controller on the nehalem based and barcelona, shanghai, istanbul, magny cours architecture. Is the performance gap in stream, everest, sandra etc ... only due to the memory controller even after the balancing memory resources (same number of memory channels (lynnfield), frequency and memory timing) or is there something else important. The reason to ask this question is that my work is concerning about the HPC computing with the memory demanding applications (calculations of electronic structure in molecules and solids), where we see the strong correlation between the performance and the memory throughput. Is really Nehalem based systems so good for the memory demanding applications? And the reason is the excellent on-die memory controller on Intel side or AMD cannot utilize all memory resources?