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News Intel to develop discrete GPUs

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NTMBK

Diamond Member
Nov 14, 2011
8,841
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I'm going to lean on DG1 sharing system memory, if that rumor is accurate. It'll be an easy way for a dGPU to save on costs.

Of course rumors have been quite inaccurate and exaggerated on lots of things. Weren't there rumors that it'll use GDDR5/6 with 96-bit interface as well? With 96EUs @ ~1.5GHz that kind of bandwidth is perfect.
Sharing system memory would be a disaster. You would need to route every memory request over PCIe, and Intel only put a PCIe x4 connection on Tiger Lake... It would perform worse than the integrated graphics.
 
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Shivansps

Diamond Member
Sep 11, 2013
3,062
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Sharing system memory in total is 100% impossible, it would perform far worse than a IGP. what they COULD do is to have 1GB of memory and market the card as "up to 4GB" and use the fast 1GB of VRAM as a cache... that is actually possible and it would be faster than a igp, in fact some cheap nvidia oems did this with low end cards in the past that actually had 128/256mb of vram and they marketed them as "up to 1GB".
 

ModEl4

Member
Oct 14, 2019
37
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It would be interesting to know what deal Raja closed with Intel when they hired him. What are they expecting regarding market share/ margins/execution etc.
Lol, imagine the following conversation circa 2017 at the interview:
Raja "GPU space is very different than CPU, the competition is fearless, as you know we launched in Q2 2016 a 232mm2 256bit 8GB design on a leading process at $239, are you really willing to be competitive with these guys and launch after say five years a 16GB 232mm2 256bit card on a leading process at $239?
Intel: "Yes we know, you have a deal, now put it there!"
lol, I'm just messing around, but if the conversation went anywhere near, how can he not be successful?
I am joking of course, please don't start writing about the greater plan, HPC importance, or drivers and optimization etc...
 

ModEl4

Member
Oct 14, 2019
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So it's probably Tigerlake die with disabled cpu-cores?
Is it possible though? I mean I don't know, but the last 2 years Intel had a serious problem fulfilling demand and now they just wasting die space like that? Or the 10SF yields are so bad?
 

IntelUser2000

Elite Member
Oct 14, 2003
7,164
1,732
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So they want to have DG2 with 128EUs as the lowest end and with GDDR6 interface, but also have DG1, that's the same one in Tigerlake but everything else except the memory controller, and GPU cut off entirely.

@naukkis There's nothing preventing them making the die only having the GPU and the LPDDR4x interface. It'll be small like 50mm2. They sold Atoms with 25mm2 dies, and the just announced Elkhart Lake IoT Atom is 60mm2 for the CPU.

Still its a very different strategy from what normal GPU vendors use. Normally you'd just cut half the memory interface.

The only guess I can give is that this allows for fast TTM, since DG2 is still a ways away(as in late 2021).
 

naukkis

Senior member
Jun 5, 2002
365
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@naukkis There's nothing preventing them making the die only having the GPU and the LPDDR4x interface. It'll be small like 50mm2.
There is. They need die space to be able to use 4*32 bit LpDDR4x memory interface. So if they make GPU-die they would use 64 bit GDDR5/6 memory interface to be able to make smallest possible die for only 96EUs. So it is probably just Tigerlake with disabled CPU-cores, 10nm yields still sucks and they can salvage something - although 96EU GPU is worth about nothing.
 
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mikk

Platinum Member
May 15, 2012
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No way they will use the Tigerlake die for DG1 with just disabled parts, no way. They have to disable a lot more than just CPU cores, look at the Soc.
 

jpiniero

Diamond Member
Oct 1, 2010
8,397
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No way they will use the Tigerlake die for DG1 with just disabled parts, no way. They have to disable a lot more than just CPU cores, look at the Soc.
We are talking about 10 nm here. There's going to be plenty of chips to salvage from. As far as I can tell Intel doesn't have any Tiger Lake SKUs with an intact GPU but disabled CPU cores.
Have to agree that a real monolithic die would use GDDR6.
The other option goes back to the Rocket Lake using chiplets rumor. 10 nm PCH + 10 nm GPU die.
 

mikk

Platinum Member
May 15, 2012
2,909
729
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This is a waste of 10nm capacity because there are large parts unrelated to CPU and GPU wich would be useless for DG1 and therefore this idea is pure madness. Also the yield issues (if they still have) seem to be more GPU affected, the amount of Icelake devices in the market without a fully enabled CPU variant (Core i3) are rather small, they didn't even need a Pentium/Celeron lineup. Tigerlake shouldn't do worse in this regards.

RKL-S is a fully 14nm chip, the chiplets rumor for a tiny GT1 graphics never made sense from the beginning. It only made sense for a GT2 but since RKL-U has been cancelled this is not even an option.
 

IntelUser2000

Elite Member
Oct 14, 2003
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This is likely Gen12 HP based. 128 EUs and 1024 shaders processors--> it must have 8 threads per EU. Gen12 LP only has 7 threads per EU. Performance looks good for only 1.4 Ghz.
The picture doesn't show anything relating to 8 threads.

It says 128 cores and 1024 SPs. The Xe LP shows 96 cores and 768 SPs. It has an 1:8 relationship because cores in Intel case is an EU, and each EU can process 8 FP instructions.
 

mikk

Platinum Member
May 15, 2012
2,909
729
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11th Generation Intel® Core™ i7-1165G7 Processor
Windows 10 Home 64-bit
Intel® Iris® Xe Max Graphics - 4GB LPDDR4X VRAM
16 GB of onboard LPDDR4X system memory
8 GB / 16 GB LPDDR4X 4266
4GB VRAM (video memory)

4GB LPDDR4x confirmed and it's a discrete memory by the looks of it, it clearly says 4GB VRAM.

Some more Asus pictures: https://www.laptopspirit.fr/276992/asus-vivobook-flip-14-tp470ea-tp470ez-ultrabook-14-tactile-tablette-tiger-lake-iris-xe-dg1-thunderbolt-4-numpad.html

There are big air intakes on the left side, the cooling is much bigger than usual. In might also help Tigerlake, maybe a true 28W CPU.
 
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stebler

Junior Member
Sep 10, 2020
7
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According to the latest version of the Windows driver, DG2 supports AV1 encoding.

Code:
.?AVDecodeAv1PipelineAdapterG12@@
.?AV?$_Ref_count_obj2@VAv1PipelineG12@decode@@@std@@
.?AVEncodeAv1VdencPipelineAdapterG12@@
.?AVEncodeAv1VdencPipelineAdapterG12Dg2@@
.?AV?$_Ref_count_obj2@VAv1VdencPipelineG12Dg2@encode@@@std@@
.?AVAv1DecodePktG12@decode@@
.?AVAv1PipelineG12@decode@@
.?AVAv1DecodePicPktG12@decode@@
.?AVAv1DecodeTilePktG12@decode@@
.?AVDecodeAv1FeatureManagerG12@decode@@
.?AV?$_Ref_count_obj2@VAv1VdencPipelineG12@encode@@@std@@
.?AVAv1VdencPipelineG12@encode@@
.?AVAv1VdencPipelineG12Dg2@encode@@
.?AVAv1VdencPktG12@encode@@
.?AVAv1VdencPktG12Dg2@encode@@
.?AVAv1DecodeFilmGrainG12@decode@@
 

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