Intel to Detail 14nm Process on August 11

[witeken]

You know, this 2.2x value was calculated by a person at SeekingAlpha, Intel didn't make any statements about 22nm vs 14nm except that it's more than usually. According to this calculation, they are ~35% ahead like they say in that slide.

 

[AtenRa]

You know, this 2.2x value was calculated by a person at SeekingAlpha, Intel didn't make any statements about 22nm vs 14nm except that it's more than usually. According to this calculation, they are ~35% ahead like they say in that slide.

Using Intel's cost per transistor formula used to calculate cost/transistor(picture bellow), if Area density is lower or at 2x ,then cost per transistor scaling is getting higher not lower. So they used 2.2X area density to arrive at higher scaling cost per transistor at 14nm.

But according of their formula, 22nm to 14nm only brings 49,4% density. That is even bellow 2X area density. :whiste:

 

[Homeles]

Using Intel's cost per transistor formula used to calculate cost/transistor(picture bellow), if Area density is lower or at 2x ,then cost per transistor scaling is getting higher not lower. So they used 2.2X area density to arrive at higher scaling cost per transistor at 14nm.

But according of their formula, 22nm to 14nm only brings 49,4% density. That is even bellow 2X area density. :whiste:

They're also reducing fin count in many of their circuits. >2x is very feasible when taking that into account.

 

[witeken]

They're also reducing fin count in many of their circuits. >2x is very feasible when taking that into account.

I think that's already taking into account. The last person was talking about 20% more transistors to get a 0.63x scaling. 0.51 * 1.2 = 0.61 ~ 0.63.

 

[AtenRa]

That happens when you mix PR and engineering. :thumbsdown:
And what about the electrical characteristics of 14nm ??? they were only focused at area density. They had all the Ioff, IDsat Gate voltages etc illustrated for the 22nm, nothing on 14nm. :\

 

[witeken]

What are you complaining about? That was not the scope of the presentation. Intel's slides were much more closer to reality than TSMC.

 

[AtenRa]

Have a look at the 2012 IDF and 22nm Tri-gate and you will see the difference. 2014 was so PR that made me sad. I was expecting more engineering than PR, Yesterday it was IDF 2014, not Investor meeting 2013. 😛

 

[witeken]

IDF 2014 is in September. The presentation 2 days ago was mainly about Broadwell-Y.

 

[Homeles]

That happens when you mix PR and engineering. :thumbsdown:
And what about the electrical characteristics of 14nm ??? they were only focused at area density. They had all the Ioff, IDsat Gate voltages etc illustrated for the 22nm, nothing on 14nm. :\

We'll probably see that at IEDM.

 

[AtenRa]

yea my bad, that was not IDF 😳

 

[TuxDave]

Intel 22nm = 7200
Intel 14nm = 3640

Intel 14nm = 49,4% smaller than 22nm

So then, Intel's 14nm didn't scale down 2.2 times over 22nm like they communicated using a different slide , but not even 2x according to Intel's own measurements ?? 🙄

Those process PR wars are the worst ive seen. :thumbsdown:

1.94x (derived from a rough estimate) vs 2.2x (a claim). From someone not as qualified as Bohr, the rough estimate is reasonable but it's sort of like saying: "Oh you can roughly estimate a person's weight by his height * pants size^2 vs a reference model because everyone's a cylinder and uniform in density". Both are pretty good for getting a hand-wavy estimate.

That's how I see the 1.94x estimate. At work, my hand-wavy estimates always come with a +/- 20% (which is made up and not derived from anything) to demonstrate the typical case just to get people off my back to come up with quick estimates vs a more detailed analysis to follow. Maybe I'm just a sloppy engineer. 😛

 

[Idontcare]

1.94x (derived from a rough estimate) vs 2.2x (a claim). From someone not as qualified as Bohr, the rough estimate is reasonable but it's sort of like saying: "Oh you can roughly estimate a person's weight by his height * pants size^2 vs a reference model because everyone's a cylinder and uniform in density". Both are pretty good for getting a hand-wavy estimate.

That's how I see the 1.94x estimate. At work, my hand-wavy estimates always come with a +/- 20% (which is made up and not derived from anything) to demonstrate the typical case just to get people off my back to come up with quick estimates vs a more detailed analysis to follow. Maybe I'm just a sloppy engineer. 😛

Not to mention that min design rule based density estimates communicate absolutely nothing regarding drive currents, voltages, leakage, power consumption, clockspeed, etc for circuit built with those min design rule geometries.

It is so easy to get people worked into a lather over a few relatively meaningless numbers when the rest of the parametric characteristics are unknown.