- Feb 18, 2001
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...on the Itanium! Ha! Bet you thought I was going to talk about the Conroe or something didn't you?
The next Itanium, codename Tukwila, will be quadcore, have 24MB of cache, an onboard memory controller, and point-to-point differential signalling interconnects.
real world tech
The next Itanium, codename Tukwila, will be quadcore, have 24MB of cache, an onboard memory controller, and point-to-point differential signalling interconnects.
According to several slides at an HPC conference in Asia, Tukwila will be a quad core part, confirming earlier rumors reported by Ashlee Vance of the Register and Charlie Demerjian of the Inquirer. Tukwila features an on-die FB-DIMM memory controller, which will lower access latency. The FB-DIMM controller likely supports 4 channels of memory, possibly more. As a result of the lower memory latency, Tukwila requires less cache than its predecessor. Montecito featured 27MB of cache, for two processors, while Tukwila is reported to have 6MB of L3 cache per core, or 24MB for each MPU. Preliminary diagrams also indicate that there is on-die switch for traffic between the four cores and caches on each chip. Tukwila will also feature the debut of the Common Systems Interconnect or CSI. CSI is a low latency, point to point, serial interconnect that uses differential signaling.
real world tech