Discussion Intel Titan, Razor and Serpent Lakes Discussion Threads

[adroc_thurston]

So they are reintroducing SMT to the P-cores?

yeah?
How is this news.

 

[Geddagod]

yeah?
How is this news.

I always assumed coral rapids would be unified core since A) I didn't expect P cores to go back to SMT after canning it B) fits the general timeline (2028-2029).
Now that you do mention it though, I remember you protesting that all the way back from the q2 2025 Intel earnings call talk here.

 

[511]

I always assumed coral rapids would be unified core since A) I didn't expect P cores to go back to SMT after canning it B) fits the general timeline (2028-2029).
Now that you do mention it though, I remember you protesting that all the way back from the q2 2025 Intel earnings call talk here.

well it's 2029 for unified 2030 is late

 

[adroc_thurston]

I always assumed coral rapids would be unified core since A) I didn't expect P cores to go back to SMT after canning it B) fits the general timeline (2028-2029).

uh, no.
Unified Core is a 2030 affair.

well it's 2029 for unified 2030 is late

Q1'30 is the best case.
I mean it's barely left pre-definition now.

 

[511]

Q1'30 is the best case.
I mean it's barely left pre-definition now.

Well sucks tbh they should have worked it on Sooner P core has been sucking for a while Golden Cove is the only good one in the last decade I only heard rumor the IPC Target is same as Royal

 

[adroc_thurston]

I only heard rumor the IPC Target is same as Royal

naaa not even close.
But it's reasonable (under the assumption they can fix their logic and physical design by 2028).

 

[511]

naaa not even close.
But it's reasonable (under the assumption they can fix their logic and physical design by 2028).

what is it than according to you? their logic design is okay but Phy Des sucks must be due to the years of Intel custom tooling

 

[poke01]

Guys, there is a dedicated thread for unified core here:

Discussion - Intel’s Unified Core: Hammer Lake

This is the “final architecture” that Intel has to prove it can survive with a profit on the server and client side. It currently looks like it’s coming out in 2028 after Razor Lake in 2027. https://www.zhihu.com/question/1920608785766028968/answer/1922041831182569570

forums.anandtech.com

Maybe @poke01 could amend the thread title with Hammer Lake?

Done

 

[DrMrLordX]

Finally, Intel will partner with NV to build mega APU to compete with AMD's Halo and NV's ARM APU. Yes, NV most likely only providing iGPU tile similar to GB10, let Mediatek or Intel designing their own CPU+SoC....

It is too early to speculate, but GB10 should show us what to expect with LPDDR6, next generation memory interface.





GB10: S-Die refers to SoC die; G-Die refers to GPU die
View attachment 130556

Mediatek IP ???

 

[Geddagod]

Well sucks tbh they should have worked it on Sooner P core has been sucking for a while Golden Cove is the only good one in the last decade I only heard rumor the IPC Target is same as Royal

If this is true what's the point of cancelling royal lmao

 

[DrMrLordX]

If this is true what's the point of cancelling royal lmao

Royal sucked (apparently).

 

[Tigerick]

Mediatek IP ???

You meant successor of N1: N2?

Some people still not getting the codename right. As Jensen said:

We also have a new Arm product that's called N1," said Nvidia CEO Jensen Huang at the press conference for the newly announced Intel-Nvidia alliance. "That processor is going to go into the DGX Spark and many other versions of products like that. And so we're super excited about the Arm road map, and this doesn't affect any of that.

I think N2 CPU+SoC die should be fully designed by NV. NV let Mediatek designed the N1 SoC most likely NV wants to focus resources on the Olympus core with SMT. N2 ARM SoC should be much more interesting with Vera SMT + Rubin with 384-bit LPDDR6 memory.

 

[Thibsie]

Fully designed by nvidia ?
Should fail then. xD

 

[511]

If this is true what's the point of cancelling royal lmao

For not sucking in PPA and Royal targets wee like 2-2.25X IPC of Raptor cove iirc so it would be even more IPC than Apple Cores by a decent amount butt will it be in 2029-30 we will have to see

 

[Geddagod]

For not sucking in PPA

Yes, there's more faith in a combination of the P-core and E-core team, both of which aren't even as good as stock ARM btw, not to mention Apple + Qualcomm...
To beat anything new in PPA.
And as I said before, area is very arguably the least important factor in PPA with chiplets now, what people call "industry leading cores" are actually the largest with Apple in terms of logic core area, which is what the main point of contention apparently was with Royal...
But the much more important aspect of power is where both the E-core and P-core teams have traditionally sucked.

and Royal targets wee like 2-2.25X IPC of Raptor cove iirc so it would be even more IPC than Apple Cores by a decent amount butt will it be in 2029-30 we will have to see

I mean if royal targets were the same as unified core IPC targets this wouldn't have mattered, right?
It would be more believable if you said 1T perf targets were the same, and unified core went the more traditional route of having similar Fmax as their already pre-existing cores, or maybe a marginal regression.

 

[adroc_thurston]

And as I said before, area is very arguably the least important factor in PPA with chiplets now

pipe down, server designs need good area.

 

[Geddagod]

pipe down, server designs need good area.

they deff do not with chiplets now making reticle limits obsolete...
and gen on gen core count improvement scaling is supposed to start stagnating dramatically...
and cache configs (like apple, qualcomm, and tenstorrent) starting to matter more and more for area than the logic core area of the core itself....

One can already kinda see this currently with Intel spending a relatively high area on AMX per core when there is no shot AMX is that important, especially not rn/yet.
Also, die shrunk X925 edit : X4, the tiny X4 in the mediatek 9400 proves you can dramatically improve area of a very high IPC core while also keeping low v/f power attributes very similar, important for server.

 

[adroc_thurston]

they deff do not with chiplets now making reticle limits obsolete...

This is the part where you stop and re-think the stuff you've just poasted.

and gen on gen core count improvement scaling is supposed to start stagnating dramatically...

idk you don't really need moar cores per socket to win. See Venice.

and cache configs (like apple, qualcomm, and tenstorrent) starting to matter more and more for area than the logic core area of the core itself....

Apple and Qualcomm have toddler-style client caches that would crumble into bits under your average server workload. Don't.

One can already kinda see this currently with Intel spending a relatively high area on AMX per core when there is no shot AMX is that important, especially not rn/yet.
Also, die shrunk X925 edit : X4, the tiny X4 in the mediatek 9400 proves you can dramatically improve area of a very high IPC core while also keeping low v/f power attributes very similar, important for server.

word soup.

 

[Geddagod]

This is the part where you stop and re-think the stuff you've just poasted.

This is the part where you spell posted right lol

idk you don't really need moar cores per socket to win. See Venice.

Exactly my point, core count matters less and the quality of each core is starting to matter more. Area's biggest limitation would have been to core count, which matters less now.

Apple and Qualcomm have toddler-style client caches that would crumble into bits under your average server workload. Don't.

Doesn't Apple have those NDA'd server processors they use for their own internal workloads?
And Qualcomm apparently are gonna use these cores, and presumably the same cache hierarchy, to enter the server market eventually too.
I mean even if they do have to like dramatically improve the cache capacity of the cluster, the area savings you get by eliminating the LLC as a whole is immense enough to compensate.
You also have tenstorrent using the same cache hierarchy and also aiming for server skus.

The main limitation appears to be that you need a bunch of mem bandwidth to compensate for the lower total cache capacity, but if core count scaling is stagnating anyway, you also won't have to have a massive amount of mem channels then to keep up core count scaling with AMD/Intel.

word soup.

Look at a die shot of SPR. AMX is a good bit of pretty much wasted area. And they kept AMX.

 

[adroc_thurston]

his is the part where you spell posted right lol

no.

Exactly my point, core count matters less and the quality of each core is starting to matter more. Area's biggest limitation would have been to core count, which matters less now.

Area matters more than ever now, given each mm^2 yielded costs more each node.

Doesn't Apple have those NDA'd server processors they use for their own internal workloads?

It's standard Mx Max stuff and it sucks.

And Qualcomm apparently are gonna use these cores, and presumably the same cache hierarchy, to enter the server market eventually too.

Kind of. It sucks a lot too (and so did Dunnington).

I mean even if they do have to like dramatically improve the cache capacity of the cluster, the area savings you get by eliminating the LLC as a whole is immense enough to compensate.

not how it works.
Toddler caches can't handle workloads that spill into L2 (which in server is ~most of them). Infinite L2 trashing especially on i$ side, just what everyone wanted.

You also have tenstorrent using the same cache hierarchy and also aiming for server skus.

meme lolcow startups that shipped 0 parts ever do not count. they don't even have human rights as far as server multiprocessors are concerned.

The main limitation appears to be that you need a bunch of mem bandwidth to compensate for the lower total cache capacity

The main limitation is going back to Dunnington (or Woodcrest if you're really into having no real LLC) sucks.

Look at a die shot of SPR. AMX is a good bit of pretty much wasted area. And they kept AMX.

Who cares about Intel, they're completely irrelevant in server.

you also won't have to have a massive amount of mem channels then to keep up core count scaling with AMD/Intel.

man please stick to phones or whatever.

 

[Doug S]

man please stick to phones or whatever.

I know it is boring to back up your trolling with reasoning or links or really anything other than giant multiquote posts full of "you're wrong, trust me bro" and liberal application of the word "sucks" but how about you try something crazy like actually contributing to forum discussion with your posts as your new year's resolution?

 

[adroc_thurston]

I know it is boring to back up your trolling with reasoning or links or really anything other than giant multiquote posts full of "you're wrong, trust me bro" and liberal application of the word "sucks" but how about you try something crazy like actually contributing to forum discussion with your posts as your new year's resolution?

This is useless word soup.
If you have anything to say about the prospect of using client caches in server, do it, otherwise lol

 

[Joe NYC]

I think N2 CPU+SoC die should be fully designed by NV. NV let Mediatek designed the N1 SoC most likely NV wants to focus resources on the Olympus core with SMT. N2 ARM SoC should be much more interesting with Vera SMT + Rubin with 384-bit LPDDR6 memory.

Is that known (or just speculation), that Vera CPU is going to use LPDDR6?

 

[Joe NYC]

This is the part where you stop and re-think the stuff you've just poasted.

(he posted that core sizes are now free to grow because of chiplets (in order to gain better performance)

idk you don't really need moar cores per socket to win. See Venice.

Seems a little contradictory.

Unless you think that with some magical skills, more performance (IPC + higher clocks) can be obtained from the same area?

BTW, from the last few products AMD released, both CPU and GPU, cramming more transistors per area seems to be one of AMD's super powers. But there is a limit of how far that can go.

 

[adroc_thurston]

(he posted that core sizes are now free to grow because of chiplets (in order to gain better performance)

chiplets aren't a magic bulletjuice that magically lowers cost per xtor for a given process node.

Unless you think that with some magical skills, more performance (IPC + higher clocks) can be obtained from the same area?

Yeah dawg, server platforms aren't just IPC and clocks.