Nah man. Given enough die area and the willingness to take a hit on power and frequency, backporting can start at any time. Architecture, RTL and schematics are process agnostic. The issue with the Intel design has always been its tools/methodology being in-house and only working with the Intel process.Decoupling was EXACTLY done so you could backport. Bringing it to a next gen process is much easier. It was very clear from the words used in the interview that they wanted to prevent a future repetition of stagnation in architecture when f.i. 7nm also turns out problematic.