Intel Sandy Bridge-EP versus AMD Interlagos

[ilkhan]

As long as you call each module a core when marking them, I don't care. But everything I've heard says that the "2c" parts are 1 module. If thats wrong, its my error.
JFAMD- *IS* that wrong?

 

[Sp12]

As long as you call each module a core when marking them, I don't care. But everything I've heard says that the "2c" parts are 1 module. If thats wrong, its my error.
JFAMD- *IS* that wrong?

But each module is two cores. They have shared L2 and can combine the their two 128-bit FP ops into a single 256.

You can't market a module as a single core, it has two separate integer cores, and one splittable FP unit.

 

[Idontcare]

As long as you call each module a core when marking them, I don't care. But everything I've heard says that the "2c" parts are 1 module. If thats wrong, its my error.
JFAMD- *IS* that wrong?

ilkhan, its really a matter of splitting hairs over the duplicity (or lack thereof) of parallel processing capabilities when it comes to the entire breadth of the ISA.

If Intel came out with some new extension, say SSE 6.0, but they opted to incorporate the new ISA extensions in a heterogeneous architecture such that the "processor" you bought was merely capable of executing/retiring two SSE6.0 instructions per clock would you really worry about whether the rest of the "processor" was sub-divided into 2 cores or 4 cores or 6 cores for the other 99% of the instructions in the ISA?

Of course you would, you'd buy the processor based on how it's "cores" were arranged to handle today's application but you wouldn't so much mind if tomorrow's apps (recompiles for SSE6.0) only had moderate performance while being compatible nonetheless.

This may be an absurdly poor analogy, the is shining and the weather is bitchen here so I found some margaritas a little earlier than usual, but it seems to me we are just needlessly splitting hairs here over the technical details of how AMD's bulldozer architecture supports the instruction throughput of its supported ISA.

Cores have really become a fuzzy product definition. This was sort of true when we had shared IMC's and shared caches across within-socket cores. Now that we are entering the phase of CMP the laymen's notion of a core is all the less relevant in terms of capturing the essence of a performance metric. (as was said of clockspeed when Intel went the low-IPC high-GHz route)

 

[Ares1214]

To be honest, i dont care what they call it as long as it beats Intel in perf/$, perf/watt, perf/temp, and overclocks just as high. Modules or cores, as long as once you put them all together its a winner.

 

[WhoBeDaPlaya]

FP units have been a part of the "core" since the 486 days. So I think most people will define core to include a FP unit.

Hello 486 SX (not to mention IBM's 486 SLC2).

 

[Edrick]

Hello 486 SX (not to mention IBM's 486 SLC2).

The Intel's i486SX was a modified Intel 486DX microprocessor with its floating-point unit (FPU) disconnected. All early 486SX chips were actually i486DX chips with a defective FPU. If testing showed that the central processing unit was working but the FPU was defective, the FPU's power and bus connections were destroyed with a laser and the chip was sold cheaper as an SX; if the FPU worked it was sold as a DX

SX chips still had a FPU, it was just disabled. But I do not think this is important in the context of this thread.