Think you are underselling using that much 10 nm silicon kills the margins. AMD jacking up Epyc prices should help the situation but it's still going to be rough.
It kills the margins when they are still having yield issues which especially effects larger dies. ICL-SP is smaller than CML-SP and should be significantly more performant and allow Intel to sell for significantly higher prices today, yet they are saying ramping ICL-SP is hurting margins. ICL-SP is also about the same amount of 10 nm silicon as AMD uses N7 silicon for Milan and yet Epyc margins are through the roof and they still have to include the IOD on top of that. SPR will have the most amount of advanced node silicon on package but as I already mentioned, it is broken up into 400 mm2 tiles with 1 core per tile already disabled for yield. SPR should allow Intel to charge even more than ICL to make up for the increased silicon. AMD is expected to use 7N/6N for Genoa IOD as well as a more advanced 5N on 12 CCDs for close to 1300 mm2 total silicon area. Do you think we will be talking about AMD's decreasing margins due to Genoa? Obviously chiplets help with yield, but that doesn't change my original post about Intel still having yield issues for larger 10 nm/7 dies.