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Intel plans 0.04um Core for 2007

thorin

Diamond Member
Intel Researchers Build World's Fastest Silicon Transistors

"SANTA CLARA, Calif., June 11, 2001 - Intel Corporation researchers have demonstrated that there are no fundamental barriers to extending Moore's Law for another decade by building the world's fastest silicon transistors. These transistors -- featuring structures just 20 nanometers (nm) in size -- will allow Intel to build microprocessors containing a billion transistors, running at speeds approaching 20 gigahertz and operating at less than one volt in approximately 2007.

The 20 nm transistors, developed by researchers from Intel Labs, are 30 percent smaller and 25 percent faster than the industry's current fastest transistors, also developed by Intel researchers within the last year. (Note: A nanometer is one-billionth of a meter). Smaller transistors are faster, and fast transistors are the key building block for fast microprocessors, the brains of computers and countless other smart devices. These transistors will be the basis of Intel's 45 nanometer (0.045-micron) process generation, which the company plans to have in production in approximately 2007.

... The gate oxides used to build these transistors are just three atomic layers thick. More than 100,000 of these gate oxide layers would need to be stacked to achieve the thickness of a sheet of paper.

Also significant is that these experimental transistors, while featuring capabilities that are generations beyond the most advanced technologies used in manufacturing today, were built using the same physical structure and materials used in today's computer chips. Intel plans to use a different class of gate oxide material by the time these transistors go into production."

Thorin
 
Sounds good, but i saw a segment on CNBC this morning that said that IBM has the fastest transistor? Can anyone confirm this?
 
"The gate oxides used to build these transistors are just three atomic layers thick. More than 100,000 of these gate oxide layers would need to be stacked to achieve the thickness of a sheet of paper"

That is just sick...


When some people are doing that kind of research, it makes the rest of us look pretty dumb, uh?
 
Yeah, and I'm PLANNING on having a 12" ____. Except mine may take a little while longer. 😉

No flames, just stupid humor 🙂
 


<< Sounds good, but i saw a segment on CNBC this morning that said that IBM has the fastest transistor? Can anyone confirm this? >>



I thought I heard today on TechLive that some company- either intel or IBM, has made some 100ghz chip or can theoretically make a chip of that speed or something like that.
 
And Im going to be richer then my dreams in 2007. Sorry but I hate this hype crap. Who cares about 6 years from now, there is SO much that could change between now and then. Ask Rambus what they think theyll have in 6 years and theyll likely tell you theyll be ruling the world hehe. Tell me whats coming next year... fine and even that can change... tell me whats going to happen in 6 years and your just speakin out your arse.
 
Its kickass improvements in die-resolution that make me want separate plug-ins for FPU and ALU units. Its getting to the point of bloat as far as what is in individual processors. Multimedia extentions could be separated. Cache, FPU, and ALU units could be seaparate. You could put your money into the part of your system that needs it and go with the budget options for the less important sub-systems.
 
Of course, you failt to mention the massively increased latencies involved with all this. VLSI is good, IMO.

The whole deal with wanting different configurations for each part....that's what COMPETITION is for....
 
??? Sorry Madrat, but that has to be your zanniest idea yet. 😉 A 32-bit ALU with two levels of carry-lookahead only has around 1000 logic gates, so with small transistors, you're going to be extremely pad limited. With 9+ execution units on current and future x86 processors, that will take up an unnecessarily huge amount of space on the motherboard. Not to mention that by removing the execution units and cache the critical path length will be increased, and the clock rate will be adversely affected. At clock rates past 1GHz, the propogation time of the electrical signals in the wires becomes very important...that's why the P4 has a drive stage at stage 5 and 20 in the pipeline. Besides, past 3-way issue superscalar, you hit a wall of diminishing returns very quickly due to the x86 ISA's inherint lack of instruction level parallelism...there would be zero tangible benefit (disregarding SMT).

Oh, one other thing...if you removed the execution units, can you imagine how many pins the CPU would have??? It would add hundreds of pins with the Athlon's 9 execution units...
 
Wing do you kmnow anything about this?

I know that you work for Intel, and i thought you might have some COOL input to tell us 😉!

Bryan
 
man if they can make that stuff kinda makes you wonder what kind of technology the goverment has, would be sweet to know 🙂
 
COOL input?

Ummm... yeah, it's awesome stuff. 😉

Really, what Intel does now with the .13um process is amazing. Sometimes it's still hard to conceive the tiny dimensions that I work with. Every now and then I laugh to myself when a co-worker and I are talking about how we are &quot;way off&quot; when something measures just angstroms out of target. (One angstrom = .0001um). Or how we are asked to target a particular thickness (+/-), again measured in angstroms.

Keep in mind that all the metrology that I do, is with a Scanning Electron Microscope.

I think that sometimes people take for granted how small this stuff is. Basically, a human hair is about 100 microns wide. So with the .13um process, we could fit well over 1000 circuits side by side on a human hair.

I'm amazed on a daily basis.
 
<<??? Sorry Madrat, but that has to be your zanniest idea yet. 😉>>

Sohcan-

Okay, you got a point on the ALU units. Seems they are the simplest part of the CPU. I think the half-adder and full-adders on an ALU are one of the few setups I understand. Of course it must be simple if I half-way understand it!

I also agree that SMT is definitely the way to go.

<<The whole deal with wanting different configurations for each part....that's what COMPETITION is for....>>

BK-

Not good enough for me. Must have more!
 
I don't know if SMT is the only way to go, especially for single threaded applications (or, applications which are thread-poor). There's also DMT, the wonderful extension to SMT by Akkary, which is for singlely threaded applications. And then there's DSMT which is SMT on DMT. Of course, that uses SMT.

Very recent research in &quot;slipstream&quot; processors intruiges me a great deal. Effectively, it's using two threads, one which is dynamically &quot;shortened&quot; by hardware, which is used to give information to the original thread, which should be functionaly identical (but unmodified). In this way, the advanced thread runs faster because it's shorter, and the trailing thread runs faster because its branches are already resolved, as are othe data dependancies. The trailing thread is used to further shorten the advanced thread.

This latter type of on-chip multithreading was first simulated on a dual CMP chip (two cores on one die), each with half the resources of a similarly equipped more robust superscalar. Many applications recieved a rather large boost in performance over the superscalar at like clock speeds, and further performance improvements could be found due to the fact that smaller CMP cores are likely to be able to run at higher clock speeds.

Of course, it is brought back to SMT again, as another variation of Slipstream processors runs of an SMT base, but this was only recently a viable option because of further abilities in reducing the length of the advanced thread.

I wrote all about FMT, CMT, CMP, SMT, DSMT, (I skipped ASDMT), and slipstreaming....of course, I doubt anybody here read it. If interested, it's at systemlogic.net, though there are a few mistakes (which will be updated, they just haven't made their way to the pages yet).

But back onto topic....one of the reasons for SMT is that it allows more functional units to actually be USEFUL, whereas they would normally show massive diminishing returns. I've read a lot of stuff about &quot;what to do with a billion transistors&quot; (I horribly butchered the titles, but I'm tired😛). SMT and its derivatives are one way in which engineers to be able to actually make effective use of the more transistors afforded by the continuance of Moores' law
 
running at speeds approaching 20 gigahertz and operating at less than one volt in approximately 2007

Wow, that's awesome. 🙂
 
BK-

I'm sure there are alot of different ways to go. SMT is beneficial for the near term, just as there are others to get over later obstacles. Pure speed will always be bottlenecked by the lack of parrallel-instruction software, right?
 
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