Originally posted by: pm
Some fab terminology (at Intel anyway, but most of these are industry-wide):
tape-in : the layout database is frozen and begins the check-out process looking for issues (such as metal density issues among many others). This is done by the team who designed the chip.
tape-out : the layout database has been checked the team and is ready for manufacturing. In the old days, the tape reel would be shipped to the mask shop. Nowadays, the files are transferred. This is also done by the team who designed the chip.
fracture : the layout database is turned into mask layers. This is done by a mask team, mask shop, or fab company
first silicon/A0 silicon/post-silicon : the very first revision of a chip
sampling : an early "beta" chip that is shipped to OEM customers for early team and system check-out
product-shipping/product ready : in theory, this means that you can buy it on the street.
stepping : a revision of a mask-set. Could be thought of as something akin to a new version of software. Steppings at Intel are designated, letter/number, such as A0, B2, C1, etc. The letter indicates a computer mask revision (all, or nearly all, layers changed), a number indicates only a few layers changed - typically metal layers. A design could go from A0 -> B0 -> C0, but more commonly goes A0 -> A1 -> A2 -> B0 or something similar. Mask sets are expensive, and the more layers changed the more time it takes to get the silicon through the fab.
So, it's not possible for anyone to have a chip without having taped it out. The mask set is required to manufacture it.
As far as comments on 45nm, etc. It is too early for anyone to conclude much of anything about 45nm. Charlie is a smart guy but he's stretching in this article. No matter who is source is, no one knows what 45nm is going to look like yet. The switch to "3D gates" will be a one-shot massive improvement in leakage, but this will just reset the leakage back to the days of 0.18um silicon in terms of leakage. Similarly a switch to "high-K" gates would be a one-time massive improvement in leakage. Either one will be a huge change to the semiconductor design, manufacturing, and - in the case of "3D gates" - the semiconductor CAD industry. It is almost certain that one of these two will occur in the 45nm or 30nm timeframe, but neither one is a "sure thing" at this point. Once the change has been made, future process steps will result in further increases in leakage... the clock will be reset back a bit, but it will start ticking down again. Neither is a permanent fix for the leakage problem, and both introduce a whole new level of complexity in and of themselves.