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Intel P3 Coppermine autopsy

cooll.. i still have 2 of them in a server chugging along.
never ceases to amaze me how small we make these things.
 
I like this picture:
0000028-1024x768.jpg


Sometimes it gets lost on people just how thin the active part of the die really is.

We tell people that if they thought of a wafer as being as tall as a 10-story building then the part of the wafer that actually holds the active circuits is merely the top 6 inches of the that 10-story thick wafer.

This photo speaks to that, you see the wafer and the bumps but the entire CPU circuitry is only faintly visible under the bumps at this scale.
 
Cool, ive hacked an athlon XP apart before by accident but never been able to see anything interesting or detailed due to lack of a microscope, interesting to see the different layers :thumbsup:
 
There's so few posts in the other one I don't see the harm in bringing up the topic again...just added the link for completeness is all. I'm not cpu mod so I'm only posting as a member, can't lock threads here.
 
There's another site that I've come across that has the guy taking apart relatively modern CPUs(you know, Pentium III/4-era and such), and taking photographs of the die. Quite detailed too. I'm pretty sure I don't have the link anywhere but I should be able to find it.
 
Do you guys know ChipWorks? They're a company that will tear down your CPUs and show you layer by layer and everything. They do SEM, TEM, the whole thing, EDAX. Costs $10k to buy those reports. The difference is this guy is kinda prying it open and destroying everything in essence while the report I read had quality cross-sections showing CMOS structures you would see in a semiconductor textbook. The stuff is right there. You could totally re-engineer a CPU with that info.... well good luck with the fab part 😀

My professor was showing us some fab stuff and opened a PDF that showed the Core i5 660 or whatever... I let out a "Holy shit" in class.
 
On a totally unrelated topic, Semiconductor Insights' blog has a very familiar name. It's like they got the idea from another site. 😀

I visited both sites, before SI had their "blog" page. I thought SI and CW was pretty much the same guys though.
 
Hmm. The die is actually quite thick.

Looks like there should be some scope for lapping of the actual die. I wonder how thin you could get it before you start to compromise the structure of the circuits.

Anyone want to donate an i7 for testing purposes?
 
Mark R said:
Hmm. The die is actually quite thick.

Looks like there should be some scope for lapping of the actual die. I wonder how thin you could get it before you start to compromise the structure of the circuits.

Anyone want to donate an i7 for testing purposes?
Click to expand...

Actually they do "thin" the wafer and the die considerably prior to packaging.

It reaches a point where the wafer/die get thin enough that their mechanical strength and rigidity can be compromised by handling and the process of packaging itself (mounting the die on the CPU PCB, not "packaging" as in shoving it into the retail box for show on the shelf 😉).

Most modern chips get thinned to the order of a few hundred microns (0.1-0.2mm), with some of the more extreme products being thinned to 50-80 microns (0.05mm - 0.08mm) for die-stacking in Nand packages and so on.

edit: for reference, a wafer is usually 800micron thick (0.8mm), some can be twice as thick depending on the venfor.
 
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