Discussion Intel Nova Lake in 2026: Discussion Threads

[eek2121]

I'm having a hard time believing Intel can put 16P cores, 32E cores, and 4 LPE on a die at less than $1000 and still turn a profit?
I am skeptical of the validity of the data of this leak. Skeptical yet hopeful...

If this turns out to be reality it will be a CB destroyer, Zen 6 would need at least 32/64 to keep up.

Yes, this "feels" like an MLID sort of "leak."

Now stop and think for a second.

What you are loudly proclaiming is that Intel ca’t make a dual CCD part, but AMD can. Does that sound right to you?

 

[igor_kavinski]

What you are loudly proclaiming is that Intel ca’t make a dual CCD part, but AMD can.

I think his concern is justified since Intel's packaging tech is more expensive than AMD's. It's going to be costly in terms of volume of product manufactured per month as I don't think they will be able to make it as quickly as AMD makes their dual CCD parts.

285K was hard to get for the first few months.

 

[csbin]

L2 Cache Shared?

https://twitter.com/x/status/1934948561369907638

 

[deasd]

I'm having a hard time believing Intel can put 16P cores, 32E cores, and 4 LPE on a die at less than $1000 and still turn a profit?
I am skeptical of the validity of the data of this leak. Skeptical yet hopeful...

If this turns out to be reality it will be a CB destroyer, Zen 6 would need at least 32/64 to keep up.

Yes, this "feels" like an MLID sort of "leak."

YES, your feeling is correct, this IS literally MLID's leak, from 20 months ago:




8+32 ARL-Refresh *DEAD* and 16+32+4 NVL were firstly mentioned by MLID.

and bLLC was also mentioned by MLID more than a year ago:

Surprised? All LEAKs appeared recently just give credit to MLID.


and what's more interesting is, Videocardz deleted the report about MLID's ARL-R and NVL rumors which was reported at Oct.2023, the link below shows 404 now:

Intel reportedly planning Arrow Lake Refresh featuring 8P+32E cores for 2025 debut - VideoCardz.com

Arrow Lake Refresh with 40 cores Intel’s latest client CPU roadmap has been presented by Moore’s Law is Dead. The video reiterates some rumors and solidifies the latest information about Intel’s plans for the next three years. However, the further we look into rumored and official roadmaps, the...

videocardz.com

Page 774 - Discussion - Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 774 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

I'm quite sure VCZ deleted this report recently maybe a month ago.

Suddenly all people include leakers around are affected by MLID which is hilarious.

 

[igor_kavinski]

Could the shared cache between the P-cores be part of the effort to enable "rentable units"?

 

[branch_suggestion]

L2 Cache Shared?

https://twitter.com/x/status/1934948561369907638

Close enough, welcome back Dunnington.

 

[DavidC1]

They were purpose made to be bad so if someone got one due to bad finances, they would dream of someday getting a "real" CPU like a Pentium or a Core i3.

My main desktop is Coffeelake generation Celeron desktop, and Kabylake-U laptop. For my purposes, I don't need anything better.

If anything, it allows people who wouldn't have got a PC at all to at least participate.

Considering majority of the West, especially North America has gravity defying amount of debt among the people, I don't think it's due to bad finances people get the value chips, especially because they have latest phones.

 

[Cheesecake16]

It's a bigger L3 pile, no 3D stacking.

If that's the case then I wonder what the L3 latency will be because one of the advantages to building vertically is that your latency propagation can be lower then building horizontally...

 

[Hulk]

It's 2t and it's not that hard on N2p.

They don't need to do anything.

Is hard.

Not true.

 

[adroc_thurston]

Is hard.

Not really.

Not true.

Very true.

 

[Io Magnesso]

I think his concern is justified since Intel's packaging tech is more expensive than AMD's. It's going to be costly in terms of volume of product manufactured per month as I don't think they will be able to make it as quickly as AMD makes their dual CCD parts.

285K was hard to get for the first few months.

However, FOVEROS has already been adopted by Meteor Lake. I think it's hard to imagine that this advanced packaging process will lead to a great bottleneck.
The story will change if you want to implement a more advanced implementation than the packaging used with Meteor or Arrow in Nova Lake…
However, personally, I assume that Intel was intentionally narrowed down the small initial shipments of Arrow Lake-S.
From a group of products that can be overclocked in the initial lot They must have poured production on the mainstay laptops and Lunar Lakes that will come out later.

 

[CouncilorIrissa]

If this turns out to be reality it will be a CB destroyer, Zen 6 would need at least 32/64 to keep up.

X3D is anything but a CB destroyer, yet people are somehow still buying 8 cores at $480, that's almost twice the price of a discounted 265K that would go for what, $279 or something a few months ago.

At the end of the day, 1t and gaming perf is king. If Intel succeed and finally design a good P-core and a decent uncore, then massive nT performance will be just a nice bonus. If they don't, no amount of cores will save them.

 

[Hulk]

Not really.

Very true.

Very good.

 

[dullard]

Very good.

What specifically is hard about it? It is actually quite easy to do. Putting multiple tiles on a CPU is fairly standard practice now. It gets harder to do well -- but that does not seem to be your argument here.

 

[511]

Intel Does GNR with Multiple CPU Tile don't they?
In the end it comes down to Interconnect/Fabric how you handle the communication.

 

[Hulk]

What specifically is hard about it? It is actually quite easy to do. Putting multiple tiles on a CPU is fairly standard practice now. It gets harder to do well -- but that does not seem to be your argument here.

Seems like an HEDT amount of transistors for a CPU priced for client. "Hard" to make economically viable is what I'm thinking.

 

[511]

Seems like an HEDT amount of transistors for a CPU priced for client. "Hard" to make economically viable is what I'm thinking.

It's not HEDT tbh it's like adding 1 more compute die in Arrow Lake

 

[dullard]

Seems like an HEDT amount of transistors for a CPU priced for client. "Hard" to make economically viable is what I'm thinking.

Intel used to do it with the X series running in the ~$800 to ~$1000 range. Heck, if you include the XE chips, they went up to $2000. They stopped that line in 2019 though. Presumably this new chip would be ~$1000 to ~$2000, but as of right now pricing is just hypothetical and you are already claiming that the hypothetical price is not viable. But, do you actually know what the price will be now?

Also, it is just putting two tiles onto one base and ignoring the heat sink. Two tiles that Intel will presumably be selling for $200 to $600 each when sold individually. And the actual cost to make them is far less than that. There is no reason that I can fathom that it would not be economically viable to put two of these tiles onto one base and sell them in the $1000s range when they can sell them individually for half that.

 

[igor_kavinski]

They are only doing the 52 core halo due to the AMD 48 thread part. That's the only reason.

Only AMD seems to take risks because they listen to their customers unlike Intel who refuses to back down from their penchant to shove hybrid cores down the throats of their customers.

 

[511]

They are only doing the 52 core halo due to the AMD 48 thread part. That's the only reason.

Only AMD seems to take risks because they listen to their customers unlike Intel who refuses to back down from their penchant to shove hybrid cores down the throats of their customers.

Bruh now their is no reason to hate on E cores in NVL you got AVX 10.2 aka 512 and improved cores as well as APX it's just nitpicking at this point.

 

[igor_kavinski]

Bruh now their is no reason to hate on E cores in NVL you got AVX 10.2 aka 512 and improved cores as well as APX it's just nitpicking at this point.

They only exist because Intel can't do HT if their life depended on it. Let's hope they are able to innovate with rentable units (if that actually debuts with Nova Lake).

 

[511]

They only exist because Intel can't do HT if their life depended on it. Let's hope they are able to innovate with rentable units (if that actually debuts with Nova Lake).

Not happening with Nova if i had to say there is no crazy stuff before Unified.

BTW what's everyone expectations for improvement in ST for Nova Lake?

 

[reb0rn]

Intel 18A Process Performance: Up to 25% Faster 36% More Energy Efficient Than Intel 3

Intel shared new information about its upcoming 18A chip manufacturing process, which is set to enter mass production later this year. According to Intel, this process offers notable improvements in both performance and power efficiency compared to its current 3nm node, known as Intel 3.

www.guru3d.com

Can they pull out so huge efficiency vs intel 3, it would be huge for MT performance, sure if E cores are dropped to ~0.8v

 

[Shmee]

The PCI-E Config is really nice View attachment 125794

Yeah I came across this article https://videocardz.com/newz/intel-n...-support-one-gen5x16-gpu-and-four-gen5x4-ssds found on the Quakecon discord

 

[511]

Yeah I came across this article https://videocardz.com/newz/intel-n...-support-one-gen5x16-gpu-and-four-gen5x4-ssds found on the Quakecon discord

NVL has integrated TB5 into platform as well which is missing here it doesn't even require retimers.