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Intel microarchitecture: Nehalem v. Skylake

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jhu said:
Depends on how you look at it. The argument that Itanium was a resounding success can be easily made.
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I'm all ears. I very much wanted it to be a success and trickle down to the workstation/desktop level. On paper it looked good, but other than that I do not in what terms it can be classified as a success.

Success for Xeon maybe. 😱
 
Edrick said:
I'm all ears. I very much wanted it to be a success and trickle down to the workstation/desktop level. On paper it looked good, but other than that I do not in what terms it can be classified as a success.

Success for Xeon maybe. 😱
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Look around. What fraction of the server and high end workstation, and HPC markets do POWER, SPARC, DEC Alpha, and PA-RISC have?

Sure, SPARC is in the Tianhe II (which is a pretty dubiously designed supercomputer anyway) and POWER will be in the new DoE computers and LLNL and Oak Ridge, but other than that? PA-RISC and DEC are dead, and POWER and SPARC are scraps of the server markets (although they are scraps with probably pretty reasonable margins)

Promises about the future improvements of Itanium without ever really delivering, and while x86-64 DID deliver on first Opterons and then Xeons, killed RISC. And that worked out realllly well for Intel.
 
Edrick said:
I'm all ears. I very much wanted it to be a success and trickle down to the workstation/desktop level. On paper it looked good, but other than that I do not in what terms it can be classified as a success.

Success for Xeon maybe. 😱
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Consider where all the other "big iron" CPU architectures all went. Alpha? PA-RISC? Dead. MIPS? In low power niches. POWER? SPARC? In niches where software license costs are significantly more than the hardware.

When Intel announced Itanium, the companies producing the other architectures basically threw in the towel. You could argue that they would have done that anyway once x86-64 took off, but Itanium certainly hastened their departure.
 
Hahaha 😀

Nah, that's fine, I meant the inter-node communication design. To talk to a node on the "other side" of Tianhe II, you have to go through a ton of nodes in the middle, there are very few direct paths. If there were a cynic in the room, they might usggest it was designed to win LAPACK and not to do real work :sneaky:

Sidenote: I was incorrect/misleading about SPARC on Tianhe II, the compute nodes are Xeons and Xeon Phis, the front end is SPARC based. So do with that what you will.
 
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After this thread turned to Atoms and past server CPUs, I thought I add something to the topic.

I made a simple animation of Oliverda's uarch diagrams to show the evolution. Of course, there are lots of changing details not seen this way, but these are part of any uarch rework, which are no simple shrinks. And even if the changes are bigger, like adding a uop cache or going to PRFs, there are lots of units not affected by this. If they get changed, this has other reasons (e.g. new power or timing targets, improvements, etc.)

intel_uarch_anim00ik2.gif

Source: http://prohardver.hu/teszt/intel_architekturak_nehalemtol_skylake-ig/nyomtatobarat/teljes.html

The language is Hungarian, but you get the picture (literally). 😉
 
I seem to remember reading at the time, before it came out, that that Nehalem was a massive redesign compared to Core2. I've probably still got the magazine articles here somewhere. On top of that they completely reworked hyperthreading.

Sandy Bridge was another leap forward, but mainly due to more registers for extensions, as well as other reasons people have already mentioned.

Since then Skylake has been the biggest reworking. Re-ordering the data paths in a way that works well at low frequencies/power draw, as well as better with less cores. Just look at Skylake i3 vs previous gen i3's.
 
Deders said:
I seem to remember reading at the time, before it came out, that that Nehalem was a massive redesign compared to Core2. I've probably still got the magazine articles here somewhere. On top of that they completely reworked hyperthreading.

Sandy Bridge was another leap forward, but mainly due to more registers for extensions, as well as other reasons people have already mentioned.

Since then Skylake has been the biggest reworking. Re-ordering the data paths in a way that works well at low frequencies/power draw, as well as better with less cores. Just look at Skylake i3 vs previous gen i3's.
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Nehalem was "just" Core2 with an IMC. Sandy Bridge was the major redesign.
 
jhu said:
Nehalem was "just" Core2 with an IMC. Sandy Bridge was the major redesign.
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I'll have to double check the details, but an IMC doesn't explain the ~30% clock for clock performance improvement over Core2.
 
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Deders said:
I'll have to double check the details, but an IMC doesn't explain the ~30% clock for clock performance improvement over Core2.
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Well, depends on the test and how it's run. From my own tests with Povray, I got a 5% IPC increase (1 thread per core) or 30% IPC increase (2 threads per core) over Core 2.
 
Which does imply some architectural change if a single core can handle more instructions at once.
 
Interesting thread!
I noted that skylake i3s are very powerful. i3-6100(51W) is fast as i7-950(130W) or i5-2320(95W) so in this sense, skylake at least in lower powered dual core chips brought huge IPC increase. However the i5-6600 is only slightly faster than previous i5s so the quad core SKUs are faster but not by huge margin.
 
Essence_of_War said:
and POWER and SPARC are scraps of the server markets (although they are scraps with probably pretty reasonable margins)
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I'm not sure power is that rare. Company I work for is deeply entrenched with IBM. We run IBM AIX and that runs on expensive POWERx Servers. Recently learned we also have storage Servers from IBM running on Power6.

But yeah, if I where in command of that datacenter, I would almost certainly change to something more cost effective.
 
Sheep221 said:
Interesting thread!
I noted that skylake i3s are very powerful. i3-6100(51W) is fast as i7-950(130W) or i5-2320(95W) so in this sense, skylake at least in lower powered dual core chips brought huge IPC increase. However the i5-6600 is only slightly faster than previous i5s so the quad core SKUs are faster but not by huge margin.
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I think this is to do with the reorganisation of the structure, and being able to handle more instructions per core simultaneously, like Jhu demonstrated with Core2 and Nehalem.

Games that show the biggest difference in the i5/i7 ranges between Haswell and Skylake tend to be CPU heavy. I don't think we've seen Skylake's full potential yet.

Much like when Nehalem came out. Some saw the huge increase, others claimed that it wasn't that far above Core2 Quads.

Now we are seeing that Core2 Quads are having difficulty in games that Nehalem still manage pretty well.

I'm probably more aware of it because my previous computer was Lynnfield based, so that's what I was comparing things to when looking at benchmarks. Most people moved on to Sandy Bridge not long after it arrived.
 
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Not Nehalem, but I find all Sandy Bridge CPUs still good and competitive today for 2016, especially faster Windows 10. You don't need a new Skylake at all.
 
I was playing games at full detail with an overclocked i5 up until 8 months ago. Only a few areas in games where it makes a huge difference, but then I run Vsync at 60hz. Higher refresh rates will see more of a boost.

Obviously I'd recommend 2nd hand sandy over nehalem but nehalem is still a sturdy platform.

Got mine running windows 10 on the downstairs computer.
 
Bit busy and can't link on phone, but I suggest looking up "instruction window" (with quotes) in reference to Skylake.
 
The problem now with SB or Nehalem is lack of motherboards, the used ones are rare and overpriced, almost everyone is selling CPUs for cheap but no mobos. That's the problem with these platforms they are basically short-lived 2 years after you just won't buy a new board anymore. And CPUs are durable so after a few years you are left with CPU and no board, and for that overpriced replacement you rather sell the CPU add the mobo cash to it and buy a new combo CPU+Board.
 
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