Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[adroc_thurston]

Or does it fall in the case of "so small that it doesn't matter"?

Indeed it does!
WCL is the designated poverty part, after all (and a good one at that).

 

[Ghostsonplanets]

Indeed it does!
WCL is the designated poverty part, after all (and a good one at that).

Huh. Surprising to see you any bit interested into an upcoming Intel product. Last time was Lunar Lake (And you were correct it would be the only meaningful part of the whole Arrow Lake Core 200 line-up).

But I can understand. Finally replacing RPL-U (cost structure) and ADL-N while being a very small or "poverty", as you say, SKU. Should be Intel volume driver for Mobile.

 

[adroc_thurston]

Surprising to see you any bit interested into an upcoming Intel product

A good product is a good product, Intel just kinda sucks at making them.

Finally replacing RPL-U (cost structure) and ADL-N while being a very small or "poverty", as you say, SKU. Should be Intel volume driver for Mobile.

Indeed, fresh new IP and a good cost target.
What the market needs above all.

 

[511]

So you don't know what will be the price of Panther Lake.

No but it is not rocket science given the die sizes and additional requirements on the Motherboard

With 3050-3060 performance it is not touching the Strix Halo, let alone Medusa Halo.


Doesn't matter how much more powerful it will be. PTL-H is going to be 128 bit bus, and only 1536 ALU GPU. Yes, it will beat, most likely, Strix Point and Medusa point, but it doesn't change that fact that it is competing in the same, mainstream market.

It is not and never going to be the Halo competition.

It will not beat the top strix halo let alone Medusa halo but Nova Lake Halo will

 

[Magio]

It will not beat the top strix halo let alone Medusa halo but Nova Lake Halo will

Has there been such a thing as a NVL Halo chip rumored? I know there's that massive CPU (16P 32E), but I haven't heard anything about a huge iGPU in NVL, have I missed something?

 

[511]

Has there been such a thing as a NVL Halo chip rumored? I know there's that massive CPU (16P 32E), but I haven't heard anything about a huge iGPU in NVL, have I missed something?

Yes NVL Mobile Halo exists it will use Xe3/Xe3P I am not sure which one to be precise but it's a halo platform from Intel for mobile.

 

[Magio]

Yes NVL Mobile Halo exists it will use Xe3/Xe3P I am not sure which one to be precise but it's a halo platform from Intel for mobile.

How big are we talking about? 18, 24 Xe3?

 

[511]

How big are we talking about? 18, 24 Xe3?

I don't know that lol the only thing I know is that it exists MLID will leak if it exists or not he is only correct about names and stuff so I will give him that

 

[511]

512 Bit Vectors on E-Cores this means AVX-512 on arctic Wolf in Nova Lake

Intel AVX10 Drops Optional 512-bit: No AVX10 256-bit Only E-Cores In The Future - Phoronix

www.phoronix.com

 

[Gideon]

512 Bit Vectors on E-Cores this means AVX-512 on arctic Wolf in Nova Lake

Intel AVX10 Drops Optional 512-bit: No AVX10 256-bit Only E-Cores In The Future - Phoronix

www.phoronix.com

Thats honestly awesome news!

.... but in that case how does it differ from AVX-512 (besides marketing speak)?

I guess it has Version based enumeration and apparently some new data movement and transform instructions (but AVX-512 has had lots of instructions added over its life cycle). So seems kinda a useless marketing renaminig

 

[511]

Thats honestly awesome news!

.... but in that case how does it differ from AVX-512 (besides marketing speak)?

I guess it has Version based enumeration and apparently some new data movement and transform instructions (but AVX-512 has had lots of instructions added over its life cycle). So seems kinda a useless marketing renaminig

I mean yeah the marketing name probably the same guy that named SSE Version it says in the image new instructions and version base checking instead of flag based vs AVX-512 I guess on e core it will be double pumped AVX-512 like on zen4 which is fine imo

 

[LightningZ71]

Reading the article just makes it sounds like AVX 10.x is just the next revision to AVX-512 and not some whole new approach. I don't this absolutely requires everything in the 'mont cores to be fully 512bits as they can still use the doubled 256 approach that's been used in other solutions in the past. This is what I most expect from them, just absolutely minimal circuitry effort to bring up the capability to keep the instruction universe homogeneous across the core types.

 

[Win2012R2]

First they dropped 128 bit support, now 256 bits - which is fine, but what's the point of AVX 10.x now when it's more or less AVX512 then?

 

[AcrosTinus]

First they dropped 128 bit support, now 256 bits - which is fine, but what's the point of AVX 10.x now when it's more or less AVX512 then?

It might be part of their de-risking approach. While a team was working on the spec the other was working on the arch and depending on how feasible the full implementation is, the spec will adapt to allow this. My inference is that they had lower confidence in the cpu-arch team and left them wiggle room, now things are looking good, hopefully.

 

[511]

AMD did the same thing Intel took the bullet for AVX-512 initially and after like 6-7 years did AMD introduced it in their CPUs

 

[Schmide]

When the magician's slight of hand is revealed the illusion fades away.

 

[Glo.]

No but it is not rocket science given the die sizes and additional requirements on the Motherboard

It will not beat the top strix halo let alone Medusa halo but Nova Lake Halo will

I don't know that lol the only thing I know is that it exists MLID will leak if it exists or not he is only correct about names and stuff so I will give him that

How can you know that Nova Lake will beat Medusa Halo, if you have no clue how many Xe cores it has, in the first place?

 

[511]

How can you know that Nova Lake will beat Medusa Halo, if you have no clue how many Xe cores it has, in the first place?

 

[Win2012R2]

It might be part of their de-risking approach.

De-risking would have been just supporting AVX-512 and focus on APX which is far more promising than AVX10 stuff

 

[511]

De-risking would have been just supporting AVX-512 and focus on APX which is far more promising than AVX10 stuff

APX is already going to be supported in Both Coyote Cove/Arctic Wolf they did not half baked this like AVX-512

 

[Doug S]

.... but in that case how does it differ from AVX-512 (besides marketing speak)?

I guess it has Version based enumeration and apparently some new data movement and transform instructions (but AVX-512 has had lots of instructions added over its life cycle). So seems kinda a useless marketing renaminig

The biggest difference is that they won't have to rename it if they ever add support for 1024 bit vectors

 

[Thibsie]

The biggest difference is that they won't have to rename it if they ever add support for 1024 bit vectors

What ? That looks like genius to me.
No really, they've been smart for at least 30 min ? Maybe Intel is on its way to recovery then.

 

[moinmoin]

AMD did the same thing Intel took the bullet for AVX-512 initially and after like 6-7 years did AMD introduced it in their CPUs

Since Intel tended to ignore AMD's input Intel usually has to "take the bullet" for new development and AMD has to follow eventually to not end up with incompatible chips.

But this evolution of AVX10 to go back to 512bit only may be a result of Intel and AMD wanting to work on aligning both companies more regarding future x86 development.

Question - Intel and AMD form x86 Ecosystem Advisory Group

I think this deserves a new dedicated thread: https://x.com/intelnews/status/1846235988277842148 Team x86 let's go In the advisory group are: Broadcom, Dell, Google, HP, HPE, Lenovo, Meta, Microsoft, Oracle, Red Hat, Tim Sweeney of Epic Games and Torvalds of the Linux Foundation. Interview...

forums.anandtech.com

 

[Joe NYC]

Intel can save some face by launching 4P+32E halo part for the rendering/video encoding/workstation crowd.

That's more like a ghetto part, not halo part. Halo part would be 16P + 0E

 

[Joe NYC]

Reading the article just makes it sounds like AVX 10.x is just the next revision to AVX-512 and not some whole new approach. I don't this absolutely requires everything in the 'mont cores to be fully 512bits as they can still use the doubled 256 approach that's been used in other solutions in the past. This is what I most expect from them, just absolutely minimal circuitry effort to bring up the capability to keep the instruction universe homogeneous across the core types.

I recall someone on this thread proclaiming that Intel's introduction of parts incompatible with AVX-512 would be a trump card for Intel, because Intel's bigger market share would instantly make the incompatible part some sort of industry standard.

That was the height of "cope" logic.

Thankfully, Intel dropped that insanity today...

https://twitter.com/x/status/1902311725703061991