Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[mzocyteae]

Arrow Lake is kinda like the bulldozer of memory performance 🤷‍♀️
High clockspeeds/numbers in AIda while low results in apps that actually are latency/bandwitdth bound? 🤣
View attachment 110267

These numbers are LOW.
Horribly L2; bad L3 if compared to Zen*.

 

[moinmoin]

Latency issue has been already there since Meteorlake and Tile based design is to blame

I guess a fair comparison point for Arrowlake would be Meteorlake then, not Raptorlake. But I can't imagine that Arrowlake doesn't have any improvements in its tile based design. What made Intel call off Meteorlake's launch on desktop, but proceed to not sufficiently improve the successor for a desktop launch either?

 

[gdansk]

I guess a fair comparison point for Arrowlake would be Meteorlake then, not Raptorlake. But I can't imagine that Arrowlake doesn't have any improvements in its tile based design. What made Intel call off Meteorlake's launch on desktop, but proceed to not sufficiently improve the successor for a desktop launch either?

Skymont is good enough that they wanted to launch it and at least outside of gaming Lion Cove is generally better than Golden Cove unlike Redwood Cove. Still Arrow Lake is poorly received due to poor gaming performance and a bunch of regressions here and there, some of which seem latency-related and others which might be scheduling problems. One can only imagine how poorly Meteor Lake S would have been received as a desktop processor with Redwood Cove and possibly even worse scheduling (presumably they fixed some bugs in the last year). If they did launch it would have to be OEM only to avoid that.

If Intel doesn't have an Arrow Lake Refresh LGA-1851 is probably a one-and-done platform because Meteor Lake was supposed to be the first but we never got it. Really, really turns me off from even considering the platform after what AMD said about AM5 through 2027.

 

[adroc_thurston]

E-cores L1 latency is 3 cycles

No?

Except all future high-ipc designs to have that 3-cycle L1 load latency.

The last of the pack was Apple, and even they went to 4c L1d for the sake of speed.

 

[511]

David Huang is testing GB on P and E cores
P core 2580 5.5 469/Ghz

Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 - Geekbench

Benchmark results for a Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 with an Intel Core Ultra 7 265K processor.

browser.geekbench.com

E core 1889 4.6 410/Ghz

265K E-core - Geekbench

Benchmark results for a Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 with an Intel Core Ultra 7 265K processor.

browser.geekbench.com

 

[cannedlake240]

Skymont still appears to be around 18% behind LNC in GB6 PPC. Idk if this is all that great...

David Huang is testing GB on P amd E cores
P core

Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 - Geekbench

Benchmark results for a Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 with an Intel Core Ultra 7 265K processor.

browser.geekbench.com

E core

265K E-core - Geekbench

Benchmark results for a Colorful Technology And Development Co.,LTD CVN Z890M GAMING FROZEN V20 with an Intel Core Ultra 7 265K processor.

browser.geekbench.com

 

[Hulk]

I presume there's little to no scheduling issue, and more of it is memory/latency issue.

If you read Microsoft Office and Adobe ranking by TPU, you can find it could be easily diagnosed as MS/Adobe test suites are memory sensitive benchmarks, and it's memory/latency issue which leads to poor performance in these test suites with Ultra 200. What's coincident is 285k is roughly on par with 14600k in gaming which is memory sensitive as well.


View attachment 110272


Latency issue has been already there since Meteorlake and Tile based design is to blame, I guess there would be nothing Microsoft or Intel can do here, and these issues cannot solved by using better memory.

What memory/latency tests do you see ARL specifically not looking good that would cause the low scores we are seeing in these memory sensitive applications?

 

[StinkyPinky]

Actually blows my mind how poor these CPU's are. They must have done internal testing, and they somehow saw it fit to release them in this state? AMD managed to tread water this year with their cpu's and STILL managed to beat Intel. That's just sad.

 

[naukkis]

No?

The last of the pack was Apple, and even they went to 4c L1d for the sake of speed.

You are right, Skymont have regressed to 4-cycle L1. Older E-cores have 3-cycle L1.

 

[GTracing]

Skymont still appears to be around 18% behind LNC in GB6 PPC. Idk if this is all that great...

469 / 410 is 13%. I'm not sure where you're getting 18%.

 

[511]

Skymont still appears to be around 18% behind LNC in GB6 PPC. Idk if this is all that great...

How is it 18% lmao it's 14% that's more than enough diffrence for Zen 5%

 

[SiliconFly]

.

 

[Hulk]

When I first heard there would be no HT in ARL I was quite sure MT was going to be a problem. Also, based on 6GHz clocks I thought ST benchmarks, which actually isolate 1 core and are able to attain that 6GHz frequency would be a problem for ARL.

But, I was under the belief that improvements in Lion Cove would mitigate the latency/memory penalty of tiles and the minimal decrease in all-core frequency coupled with the fact that quite a lot of software still only uses ~8 threads meant that ARL would do very well in test suites like MS Office. What I'm trying to communicate here is the fact that 1-2 core Turbo clocks are irrelevent generally outside of benchmarks.

What we get is the exact opposite of what I was expecting. Intel hits it out of the park with Skymont, showing us IPC gains we haven't seen since Conroe. Any latency, tiles, or whatever are overcome and then a whole bunch more. ARL is competitive in MT and better than Raptor Lake.

ST benchmark scores are pretty good as well, which I didn't expect. But when the rubber hit's the road, on actual applications, there are weak spots and Lion Cove currently is underperforming and I think letting down the ARL design. I am hoping this is an fixable issue that brings Lion Cove up a bit for Intel's sake, but as it stands right I think it's hard to make a case for the 285K as top dog when it comes to overall performance. It's still only a day from NDA so things could change.

To summarize my take on ARL at this time:
- Very good MT performance due primarily to Skymont
- Much improved efficiency compared to Raptor Lake but still a bit behind Zen 5
- Much improved temps, I don't see issues extracting full stock performance on air
- Confusing high/low on certain benchmarks (MS Office for example) that seem to indicate a bottleneck associated with Lion Cove that may be fixable with microcode or the Thread Director, but realistically I'm thinking will take an architectural change to address.

Intel will still get these in millions of systems and as Anand always said, "there are no bad products, only bad price points." Without Skymont this would have been a really bad showing for Intel.

Finally, I have to double check but I don't think Lunar Lake was doing bad in MS Office type stuff, in fact I think it excelled.

 

[gdansk]

Skymont, showing us IPC gains we haven't seen since Conroe

🤔 Coming from behind like Zen 1

 

[gdansk]

- Confusing high/low on certain benchmarks (MS Office for example) that seem to indicate a bottleneck associated with Lion Cove that may be fixable with microcode or the Thread Director, but realistically I'm thinking will take an architectural change to address.

It's (generally) Intel's director putting work on Skymont and not figuring out it should be moved to Lion Cove. Not Lion Cove's fault. Intel needs to fix this if they're keeping two different core types, regardless of what the cores are.

 

[Thunder 57]

Intel will still get these in millions of systems and as Anand always said, "there are no bad products, only bad price points." Without Skymont this would have been a really bad showing for Intel.

Anand was wrong. There are bad products. PSU's that catch fire. "Deathstar" HDD's. More recently, 7800X3D's that went up in smoke, or degrading RPL.

 

[MS_AT]

It's (generally) Intel's director putting work on Skymont and not figuring out it should be moved to Lion Cove. Not Lion Cove's fault. Intel needs to fix this if they're keeping two different core types, regardless of what the cores are.

But did anyone verify that or this is still an assumption based on weird results? I am Thread Director was supposed to have easier job with only P and E cores without HT...

 

[511]

But did anyone verify that or this is still an assumption based on weird results? I am Thread Director was supposed to have easier job with only P and E cores without HT...

Techtubers not verifing what is happening as always outside of TPU GN

 

[gdansk]

But did anyone verify that or this is still an assumption based on weird results? I am Thread Director was supposed to have easier job with only P and E cores without HT...

It is as unverified as blaming Lion Cove.
But there's a reason I avoided buying any heterogenous processors for machines that will run Windows. It takes them so long to fix things.

 

[alcoholbob]

Skymont is good enough that they wanted to launch it and at least outside of gaming Lion Cove is generally better than Golden Cove unlike Redwood Cove. Still Arrow Lake is poorly received due to poor gaming performance and a bunch of regressions here and there, some of which seem latency-related and others which might be scheduling problems. One can only imagine how poorly Meteor Lake S would have been received as a desktop processor with Redwood Cove and possibly even worse scheduling (presumably they fixed some bugs in the last year). If they did launch it would have to be OEM only to avoid that.

If Intel doesn't have an Arrow Lake Refresh LGA-1851 is probably a one-and-done platform because Meteor Lake was supposed to be the first but we never got it. Really, really turns me off from even considering the platform after what AMD said about AM5 through 2027.

Also with all the layoffs and project cancellations at Intel, it makes me shudder to think the next socket after Arrow Lake might be even worse relative to next-gen AMD offerings. Scary to think Alder Lake might be the high point of Intel for a very long time.

 

[511]

Intel's Future Depends on 4 things 18A PTL Clearwater Forest and Falcon shores in 25

 

[gdansk]

Intel's Future Depends on 4 things 18A PTL Clearwater Forest and Falcon shores in 25

I'm glad their future doesn't depend on Arrow Lake.

 

[OneEng2]

I mean I don't expect a hypothetical 9950X 3nm edition to be much more efficient except in low TDPs. Check the chart above where 285K out performs the 9950X (under 150W). And there it is the IOd which is wasting power and here Intel has an advantage due to interconnect.

Seems like a questionable approach. In the desktop and desktop replacement laptop markets, the higher performance within the power envelope will be the most important to consumers. I am not buying into this concept that this market cares about how much electricity the computer is using. Thin and light? Sure.

More importantly, I see potential for Skymont and Lion Cove in the DC products of the future where the designs are likely to be power envelope bound ..... then your argument vector starts to make sense IMO.

Overall, it's questionable. Matching 5nm Zen 4 at the same average power...

Exactly my point. For all the advantages Arrow Lake should have had, it seems to be quite a let down.

All the hype of Skymont and it's only 18% more efficient than Gracemont. N3B vs Intel 7 and all they got was 18% improvement?

Arguably 2 full die shrinks. Agree. Still, Skymont shows impressive IPC per die area .... and that isn't "nothin".

TSMC themselves gave these approximate figures for their respective processes:

N3(B): +15% perf (aka clocks at iso power/transistor count) or -30% power vs. N5
N4P: +11% perf or -22% power vs. N5

So the only area where N3B is a notable uplift over N4P is transistor density.
N3E is slightly better than N3B in terms of perf/efficiency (+18% or -32% vs. N5), but loses some density.

Additionally, the technical differences between N5 class and N3 class processes could be significant enough that a quick-n-dirty shrink doesn't necessarily give you the maximum clockspeed benefit "just like that".
In any case, a 3nm Zen5 would've likely used N3E.
But 10-15% higher clocks would mean 6.3-6.6 GHz, and I highly doubt that Zen5 would've hit that so easily.

Consumer-Zen6 with the FPU scaled back to 256bit might hit that with N3P, if we're lucky.

By these TSMC figures, a die shrink alone should be 8% lower power, but you are correct, the higher clocks would be more on the order of 5%.

... and because you are also correct that the tools are different for the different processes (libraries are not compatible), it would not be an easy shrink. I was only posing a hypothetical.

I believe I have seen that Zen 6 is targeting N3P in mid 2025. That shows that AMD has no desire to do a "shrink only" design (which makes sense).

Extrapolating from earlier IPC comparison and comparing clock rates to the OC results posted above
A non-SMT Zen 5 would yield 1588 * (57/40) * 16 = 36,204
Arrow Lake would yield 1459 * (54/40) * 16 + 1702 * (58/40) * 8 = 51,257 very close to the observed

So apparently SMT has insane yield here. Over 40%...

Spoiler: Zen 5 vs Arrow Lake CB23 IPC

View attachment 110259

It is my understanding that CB24 is much more bandwidth hungry than CB23 .... which is making me think that Arrow Lake's good showing in CB24 is more about its bandwidth than its processing prowess while CB23 seems to be more processor constrained.

Someone correct me if I am off base here.

It's the realization that this stagnation won't be fixed for 2 years.

Definitely. As I have said, I think the party is over for we enthusiasts. The days of Conroe level improvements is dead as the exponential cost of process equipment and physics has brought a halt to that performance progression.

I think the future big increases will be more targeted to specific tasks utilizing either specific new instruction sets, or specific cores designed for more specific workloads thus eliminating the need for new process equipment in order to make big gains.

E-cores L1 latency is 3 cycles. Except all future high-ipc designs to have that 3-cycle L1 load latency. For Lion Cove removal of HT probably saved that one cycle from 5 to 4 - but yet they don't have backend to fully take advantage from that lowered load latency. They need to redo whole backend to single-thread optimized to really gain advantage from removing HT.

I think that Intel can't easily add SMT back to the design. It would be a ground up work effort.

Chips and Cheese:

If Lion Cove IPC is so high above ZEN5, why doesn't it show in application performance? I am a bit baffled. I do understand that there are WAY more operations in the processor than this little chart shows. Also FWIW, XOR is most frequently used for flipping specific bits in a register IME.

Actually blows my mind how poor these CPU's are. They must have done internal testing, and they somehow saw it fit to release them in this state? AMD managed to tread water this year with their cpu's and STILL managed to beat Intel. That's just sad.

True; however, what makes it worse is that Intel essentially had a double die shrink to mostly catch up with ZEN5 which remained on the same process node (mostly).

I kind of wonder if AMD gambled on this decision as the more certain path to performance superiority over an unreleased Arrow Lake would have been to produce Zen 5 on N3E and take the increased transistor budget to enhance performance in a few key areas.

 

[OneEng2]

Intel's Future Depends on 4 things 18A PTL Clearwater Forest and Falcon shores in 25

Mostly 18A IMO. It doesn't matter how well their processors do if they can't make them at a profit.

 

[gdansk]

I believe I have seen that Zen 6 is targeting N3P in mid 2025

It's 2026H2. Or later. It can always be later.