Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Apr 1, 2022
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Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Gideon

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Nov 27, 2007
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Core Ultra 285 non-K coming. 65W TDP complete with GB6 scores. Can anyone run 9950X at 65W to compare? Be interesting to see how the 3nm scales down with power compared to the 4nm.

I hope we get more demanding benches as well, as GB6 MT score is rather useless to predict all-core workloads.

Anyway this result is rather "meh" It's about the same as a Ryzen 9600X ("65W" TDP 88W actual) both ST and MT:


And that Ryzen CPU runs at 150Mhz lower clocks. Considering the variability of GB6 (even run-to-run) I'd rather wait for other benchmarks
 

Nothingness

Diamond Member
Jul 3, 2013
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What could make sense though would be branching out the E core design into future P and E projects, with similar building blocks in the form of an "unified architecture". That would imply a P core reset, but not an unified core as the size and perf. targets would still be complementary. It would be funny in a way, since it seems to me that AMD is doing the same thing, only starting from their P core instead.
Agreed, at least partially. That can work well as long as you don't want to create really efficient/performant cores. If the common pieces are designed with a performance (exclusive) or efficiency target then they won't be optimized for the other target. You have to carefully select the parts that work well for both targets, or you'll penalise the other target. That's a difficult and time consuming exercise of balancing.

So the question is: how much performance or efficiency is Intel OK to sacrifice? Given their recent track record, I guess not much, but perhaps they've learned the hard way that winning at all costs benchmarks isn't the best thing to do.

Another thing to keep in mind is that validation and implementation costs (beyond shared block level) won't be reduced a lot by sharing.
 

Det0x

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Sep 11, 2014
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Core Ultra 285 non-K coming. 65W TDP complete with GB6 scores. Can anyone run 9950X at 65W to compare? Be interesting to see how the 3nm scales down with power compared to the 4nm.

I cannot run my current CPU @ 65w PPT in GB6 as it would be all over videocardz and WCCFTech in a matter of minuts.. (auto upload)
So it have to be someone else, or we need to wait until i pop the 9950X back in the socket.

But it should also be noted that its only PL1 thats "65w" for the 285, PL2 is whole different matter..
In terms of specifications, the Intel Core Ultra 9 285 CPU retains the same core configuration as the Core Ultra 9 285K with 24 cores based on an 8 P-Core (Lion Cove) and 16 E-Core (Skymont) design & offers 24 threads. The chip comes packed with 36 MB of L3 cache and has a base clock of 2.5 GHz & can boost up to 5.6 GHz. The chip being a 65W (PL1) design should offer a PL2 rating of around 200 Watts and was tested with just 8 GB of DDR5-5600 memory. It looks like the system was used only for boot purposes.
 

AcrosTinus

Senior member
Jun 23, 2024
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I was thinking of the same thing. And looking at the changes in lion Cove:

Like the separate schedulers for INT and FP., the removal of AVX-512 and HT in client processors, et ... it seems the two designs are already becoming more and more similar (for the client SKUs atl east).
And AVX10.2/256 be the goal of that transformation.
 
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Wolverine2349

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Oct 9, 2022
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If that's true, Arctic Wolf is probably the last separate effort before moving onto the unified one, if they just "started working on it".

What is arctic wolf? Is that supposedly the last hybrid design? SO would that be 2026. SO any merged new core design where P and e-cores are then 1 core is still a long long way off as in t least 2028 or 2029 or later. Or could it be much sooner?
 

MS_AT

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Jul 15, 2024
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And AVX10.2/256 be the goal of that transformation.
Good that AVX10.2/128 got dropped as a baseline. Does anyone know if AVX
10 is using different encoding compared to avx512? I mean will it be compatible with current AVX512 cpus?
 

Nothingness

Diamond Member
Jul 3, 2013
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Good that AVX10.2/128 got dropped as a baseline. Does anyone know if AVX
10 is using different encoding compared to avx512? I mean will it be compatible with current AVX512 cpus?
It seems to be binary compatible: https://www.agner.org/forum/viewtopic.php?t=115

Edit: I would look into the spec, but looking at anything related to x86 at that low level has the same effect on me as eating expired food.
 

CouncilorIrissa

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Jul 28, 2023
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What is arctic wolf? Is that supposedly the last hybrid design? SO would that be 2026. SO any merged new core design where P and e-cores are then 1 core is still a long long way off as in t least 2028 or 2029 or later. Or could it be much sooner?
If the work has just begun, you can be sure that you won't see any products until 4-5 years later.
 

GTracing

Senior member
Aug 6, 2021
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Good that AVX10.2/128 got dropped as a baseline. Does anyone know if AVX
10 is using different encoding compared to avx512? I mean will it be compatible with current AVX512 cpus?
Looking at the spec doc, the answer is mostly yes. (pdf warning) https://cdrdv2.intel.com/v1/dl/getContent/784267

The one major caveat is that Intel is has a new, simpler way to check for AVX-10 compatibility (section 1.3). Any software that uses this new method to check for 256 and 512 width instructions would fall back to AVX-2 on AVX-512 CPUs.
 

Josh128

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Oct 14, 2022
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I cannot run my current CPU @ 65w PPT in GB6 as it would be all over videocardz and WCCFTech in a matter of minuts.. (auto upload)
So it have to be someone else, or we need to wait until i pop the 9950X back in the socket.

But it should also be noted that its only PL1 thats "65w" for the 285, PL2 is whole different matter..

What is your current CPU? Why would it matter if a GB run gets uploaded to the browser?
 

naukkis

Golden Member
Jun 5, 2002
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Ouch. The one size fits all strikes back. Ideas for improvements moving from E-core to P-core (and vice versa) is good. Merging both designs really sounds silly.

They are axing P-core. E-core offers way more potential. Skymont ain't designed to top performance but good area efficiency, yet they are still heels on P-core. So future is build on E-core, with clustered decode and without mop cache.
 
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Josh128

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Oct 14, 2022
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Connections. Lots and lots of connections.
Interesting. So the early Nov launch rumors could be true then. AMD RARELY announce less than a month in advance of availability these days, so I would assume a launch announcement is coming quite soon.
 

DavidC1

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Dec 29, 2023
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They are axing P-core. E-core offers way more potential. Skymont ain't designed to top performance but good area efficiency, yet they are still heels on P-core. So future is build on E-core, with clustered decode and without mop cache.
Lunarlake's version doesn't perform as well but it is indeed extremely efficient. Not only that, it scales way below what any core is capable of.

It doesn't seem as area efficient as previous generation cores if the mockup block diagram sizes are real but at least in one product it's achieving efficiency goals.

Arrowlake might lose some of the efficiency for higher performance.
 

jdubs03

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Oct 1, 2013
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Just keep in mind all of that Royal Core IP up to the teams disbandment is still there for usage in future projects. So this new unified core team presents an opportunity for some of the learnings of RC to be implemented if deemed worthwhile. And from all the chatter, it does seem like there is a distinct possibility of that happening.