Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Gzxy]

It is true that those performance predictions are out of date, it's untrue that they're likely based on 20A silicon. Firstly, Intel barely expects any difference between 20A and Intel 3 results, secondly even back then the node choices would have been made.



Nobody's claiming or expecting that. I've made my own personal expectation (note: this is not a leak, just an expectation) is that LNC is targeting the same ~18% IPC uplift we've come to expect from a new core produced by Intel. But remember, those slides were indicating a ~10% ST performance uplift over RPL (5.8GHz). So with my expectation as a basis, it would imply Intel were expecting a clock regression at the time likely down to ~5.3 - 5.4GHz. I hope that doesn't sound like something totally absurd?

By the way, I fully expect Intel to actually beat that ~10% ST performance uplift, I wouldn't be surprised if it was actually conservative due to them not being totally confident on how high they could get LNC to clock. It's the first time they're trying to hit such high clocks on an external node after all.



I mean, it is what it is. I'm just going to say it now though: I highly doubt X Elite will be the fastest performing mobile part for ST (lets take Geekbench as a basis for this one, as it's the best benchmark we can probably expect swift results from reviewers in), so even if LNL can't remain ahead of it, just the simple facts that: 1. it's x86, so app compatibility won't be a concern and 2. it's an Intel product, meaning volume wise it'll likely far outstrip all of it's competitors will mean LNL will have a very solid place in the market.



I wouldn't be concerned about IPC/Clock speed shenanigans if I were you, I'd be more concerned about IOSF and ring clocks. That's the real sore spot on MTL, hopefully it doesn't carry through to ARL (I actually don't have much hope).

Remember that Apple and Nuvia can hit very high ST with much lower clock speeds. Low clock speeds aren't that bad of a problem I believe. Low clock speeds -> Can place circuits closer -> Less die space -> Can put more stuff if your die space is very low -> Increase IPC through adding more stuff in your die

Also remember how much little space Zen 4C takes because they lowered the clocks. The IPC remains the same with Zen 4. Obviously someone would think, if I gain perf by having lower clocks and more die space to work with, what's the catch? I believe that you would need to put more money to develop more your cores since you have more space available. High clocks seem to be a cheap way to increase perf and Intel took advantage of it as much as possible in the last gens. But then other problems arise since your chips become inefficient and power hogs.

 

[S'renne]

Remember that Apple and Nuvia can hit very high ST with much lower clock speeds. Low clock speeds aren't that bad of a problem I believe. Low clock speeds -> Can place circuits closer -> Less die space -> Can put more stuff if your die space is very low -> Increase IPC through adding more stuff in your die

Also remember how much little space Zen 4C takes because they lowered the clocks. The IPC remains the same with Zen 4. Obviously someone would think, if I gain perf by having lower clocks and more die space to work with, what's the catch? I believe that you would need to put more money to develop more your cores since you have more space available. High clocks seem to be a cheap way to increase perf and Intel took advantage of it as much as possible in the last gens. But then other problems arise since your chips become inefficient and power hogs.

It would be a very interesting twist if Intel starts to back down from going ham with CPU clockspeeds from ARL onwards.

Remember that 12~13th gen CPUs can still scale with overclocking, all the way to RPL-R where they can factory overclock literally 100% of their silicon for performance in exchange for their lifespan

 

[SpudLobby]

LNC being barely faster that RPL were projections probably based on really old 20A targets. Obviously most stuff we are talking here are rumors and assumptions. Think about it.
Golden Cove (2021)
Raptor Cove = Golden Cove+
Redwood Cove = ~Raptor Cove
Lion Cove = Raptor Cove+ (2024-2025)

That's bullshit. 4 years the same arch for P cores?

Also if Lion Cove is so weak that LNL will end up bad, it wont be able to even beat X Elite in ST.

I will bet it *might* be able to beat the X Elite, but just by a tad and with a higher clockspeed and much more power (in ST).

ARL and STX will be faster than both albeit at even more power than LNL most likely.

 

[SpudLobby]

I'm really doubtful that the 4 LPE cores will have much, if any, contribution to LNL's MT score. If that's true, LNC looks to be a very potent P core.

they will though. They aren’t LPE cores in the way MTL’s are. They’re off the ring without L3 but it’s Skymont on the same die and they still have a decent bit of L2 cache

 

[AMDK11]

I think it's very unlikely that GLC was created under Keller. He probably had some supervision in the later stages once he was at Intel, but very small stuff.

Need to remember that Intel was stuck for 5 years due to node issues. But IDC was already designing their uArchs well in advance because they needed to be ready for the 10nm transition, which never happened on the original timelines. (I'm not saying things haven't changed, but the ground layout was already set before the issues turned widespread)

I'd even argue that we're still seeing late 2010's designs from both Intel and AMD. Z5 was already being worked on by 2018 if we go by Clark interview. Lion Cove is probably on a similar timeline, if not even earlier.

If Keller had any significant contribution, it was probably on the fabled Royal Core. But, as Adroc, Exist and others have said, we might not even see Royal due to political issues at Intel.

So I guess we're stuck wrt "Next Big thing" until Glen Hilton reveals the "Exciting high performance project". Is it Panther Cove/Nova Lake? Something later?

From what I remember, work on SunnyCove started in 2016, so on GoldenCove somewhere around 2018. GoldenCove was completed around 2020.

 

[uzzi38]

Remember that Apple and Nuvia can hit very high ST with much lower clock speeds. Low clock speeds aren't that bad of a problem I believe. Low clock speeds -> Can place circuits closer -> Less die space -> Can put more stuff if your die space is very low -> Increase IPC through adding more stuff in your die

It's just an alternative approach to chip design. Adding more stuff on die and creating a larger core also increases power usage. Targeting lower clock speeds means your caches run slower etc. There's loads of tradeoffs taking place here, it's what makes it so damned hard.

Also remember how much little space Zen 4C takes because they lowered the clocks. The IPC remains the same with Zen 4. Obviously someone would think, if I gain perf by having lower clocks and more die space to work with, what's the catch?

Zen 4C doesn't gain perf over Zen 4, it loses it?

I believe that you would need to put more money to develop more your cores since you have more space available. High clocks seem to be a cheap way to increase perf and Intel took advantage of it as much as possible in the last gens. But then other problems arise since your chips become inefficient and power hogs.

That's just a bad assumption. Like I mentioned before, it's all tradeoffs.

 

[SiliconFly]

Obviously someone would think, if I gain perf by having lower clocks and more die space to work with, what's the catch?

The catch is lower clocks & larger die. They lose free clocks and bigger die is expensive too, not only in terms of wafer cost but also in terms of design cost & yield.

Imagine having a extremely tiny die that clocks extremely high. It'll not only be very cheap, but the yield will be thru the roof too.

 

[DrMrLordX]

MTL-U is still a good SoC for the average consumer and Intel can offer it at cheaper prices with good availability. The move to Intel 3 will also offer a 10% bump in energy efficiency.

Just to clarify, are you saying that Intel plans to rehash Meteor Lake on Intel 3 with a new name? I hadn't picked up on that from earlier in the thread, which is why I'm requesting clarification.

 

[Ghostsonplanets]

Just to clarify, are you saying that Intel plans to rehash Meteor Lake on Intel 3 with a new name? I hadn't picked up on that from earlier in the thread, which is why I'm requesting clarification.

Yes, that's what Bionic and others have claimed. ARL-U is actually MTL-U but with the Compute Tile ported to i3.

I have also seen speculation that the "ARL-U" Compute Tile will actually use Redwood Cove + (Granite Rapids implementation of Redwood Cove with IPC improvements) because the design is already done at i3. And that the GPU tile will use the new tile fabbed on N4 with XMX units added (The same tile as ARL-S/HX = 64 EUs).

https://twitter.com/x/status/1747981927020449985

"ARL-U uses Intel 3. (It's basically MTL-U ported to Intel 3)"

https://twitter.com/x/status/1747986929189335075

"It's basically the MTL cores ported to intel 3.
~10% perf per watt improvement in MT workloads"


https://x.com/SquashBionic/status/1747980520938778639

"ARL-U is basically a cheaper alternative to Lunar Lake"

 

[DrMrLordX]

"ARL-U is basically a cheaper alternative to Lunar Lake"

That's weird, and a little depressing. Though if Meteor Lake itself is any indicator, volume of ARL-U may be pretty low.

 

[coercitiv]

Zen 4C doesn't gain perf over Zen 4, it loses it?

We had the same issue with Gracemont, it was hard for some folks to grasp the idea that Golden Cove was ~80% faster in ST workloads. They knew the IPC delta, they knew the frequency delta, but somehow that did not translate well into mental performance math. The same applies here, especially for folks looking at mobile chip multithreaded performance where power limits max clocks. It's only if they consider fmax and realize that Zen 4 clocks 40-60% higher than Zen 4C that the true tradeoff of area optimization becomes apparent.

There's no free lunch, not with speed demons and not with wider cores in tighter spaces. The real wizards in this field find ways to balance both.

 

[Ghostsonplanets]

That's weird, and a little depressing. Though if Meteor Lake itself is any indicator, volume of ARL-U may be pretty low.

I think it make sense. Packaging and tile design across multiple foundries is expensive. It's best for Intel to not waste away a perfectly good product after just one generation. And if it can help with Intel endeavors on Foundry while minimizing a bit external dependency, so be it.

As for volume, Bionic stated in another tweet that ARL Mobile (Including U) will be announced at CES 25 and will launch at volume. Intel also stated last week that they shipped >5M AI PC chips (MTL) and plan to ship 40M by the end of the year (MTL + LNL combined). So I think volume shouldn't be a problem.

Intel Mobile line-up in 2025 will basically be:

<$500 - RPL U 282
<$800 - MTL/ARL U 2821 (2P + 8E + 2LPE + GT1 GFX (64 EUs)
>$700/800 - RPLR H 681
> $1000 - ARL H 6821
> $1000/$1200 - LNL 442

Edit: Also, @DrMrLordX :

Some talks.
After the brand change, INTC makes a new and last one-gen product coexist in fact, and -U product is moved to N-1 gen.
So, ARL-U is the MTL-based refresh actually, based on the P1276 series process instead of P1278.

 

[dullard]

Regarding AI driving EUV equipment needs:

Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

This has been bothering me for the last week, but I didn't take the time to respond. If you think that AI no longer drives EUV demand, can you please explain this:

TSMC founder says unnamed customers want 10 new fabs to build AI chips

More AI requires more silicon.

www.tomshardware.com

TSMC founder and industry icon Morris Chang says that customers have approached him to build up to ten new fabs for AI processors, an incredible request that speaks to an insatiable demand.

 

[Henry swagger]

GoldenCove
RaptorCove (GoldenCove with larger L2)
RedwoodCove (GoldenCove+)

RedwoodCove is not RaptorCove as there are changes to the core itself, but they are quite cosmetic. The most noticeable change is the move from L1-I 32 KB in the 8-way to 64 KB in the 16-way. The last time Intel changed L1-I from 16KB 4-way in Pentium III to 32KB 8-way in Banias was over 20 years ago. As far as I know, LionCove inherits L1-I 64KB 16-way + already existing L1-D 48KB 12-way from SunnyCove/CypressCove.

LionCove is a new core, just like SunnyCove and then GoldenCove compared to Skylake.

Besides, I don't know what you base your conclusions on. We don't know how high LionCove's IPC is. It may be, for example, 20-25%, but the clock speed is much lower. Not enough data.

From leaks and some of my guesses, LionCove has an 8-way instruction decoder(GoldenCove 6-Way), ROB entries 750-800(GoldenCove 512), and may have 6-7x ALU(GoldenCove 5x ALU), 7x AGU(4x Load + 3x Store)(GoldenCove 5x AGU(3x Load + 2x Store)), SMT4 (disabled in ArrowLake?) mainly for Xeon needs and a full 2x 512bit/4x 256bit FPU.

Plus lion cove will have 3mb l2 cache.. intel always had the single core performance crown. When was the last time they didn't have it lol

 

[Saylick]

Plus lion cove will have 3mb l2 cache.. intel always had the single core performance crown. When was the last time they didn't have it lol

Uhhh, when AMD launched Zen3 and Intel was still on Skylake based processors…?

 

[S'renne]

Uhhh, when AMD launched Zen3 and Intel was still on Skylake based processors…?

Technically...yeah lol but I do hope that Skymont would close the MT gap greatly

 

[ondma]

Uhhh, when AMD launched Zen3 and Intel was still on Skylake based processors…?

Was it really clear lead though?? I thought they were fairly close, and Intel had a clock speed advantage.
Shortly thereafter I think Rocket Lake was faster in single thread benchmarks, but the lead didn't transfer to gaming.

 

[Hitman928]

Was it really clear lead though?? I thought they were fairly close, and Intel had a clock speed advantage.
Shortly thereafter I think Rocket Lake was faster in single thread benchmarks, but the lead didn't transfer to gaming.

No, it was a pretty universal (not 100% but close) domination by Zen 3 until Alder Lake.

 

[Saylick]

Was it really clear lead though?? I thought they were fairly close, and Intel had a clock speed advantage.
Shortly thereafter I think Rocket Lake was faster in single thread benchmarks, but the lead didn't transfer to gaming.

Yeah, Zen 3 was pretty much top dog until Alder Lake.

From Anandtech's review of Rocket Lake:
https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k/7

If the benchmark doesn't take advantage of AVX-512, Zen 3 generally had the ST lead. If it's a MT test, Rocket Lake with its 8 cores stood no chance against the 5950X's 16 cores.

 

[Markfw]

Yeah, Zen 3 was pretty much top dog until Alder Lake.

From Anandtech's review of Rocket Lake:
https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k/7

If the benchmark doesn't take advantage of AVX-512, Zen 3 generally had the ST lead. If it's a MT test, Rocket Lake with its 8 cores stood no chance against the 5950X's 16 cores.

That review does not even have a 5950x in the test.

 

[Henry swagger]

Technically...yeah lol but I do hope that Skymont would close the MT gap greatly

I hope tsmc n3b can clock just as high as intel 7 ultra..

 

[Henry swagger]

Yeah, Zen 3 was pretty much top dog until Alder Lake.

From Anandtech's review of Rocket Lake:
https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k/7

If the benchmark doesn't take advantage of AVX-512, Zen 3 generally had the ST lead. If it's a MT test, Rocket Lake with its 8 cores stood no chance against the 5950X's 16 cores.

Yeah zen 3 generation was good for amd.. clock speed will be a factor on who wins in single core between zen vs arrow lake

 

[SiliconFly]

Uhhh, when AMD launched Zen3 and Intel was still on Skylake based processors…?

Skylake (and variants) were deprecated by then. Desktop was Cypress Cove (a 14+++++ backport of Sunny Cove). One of the dumbest decision in the history of computing. Intel 11th gen desktop was a monumental disaster. Thanks to Bob Swan & Murthy Renduchintala.

Mobile was Tiger Lake. It was the first decent Intel 10nm product. Decent volume. Not exactly sure how it compared with Zen 3 mobile, but I think it was pretty much equal or maybe better in some aspects. Intel 11th gen mobile was decent but a bit delayed I think.

Technically...yeah lol but I do hope that Skymont would close the MT gap greatly

Just an interesting titbit. Apparently people have forgotten the very old Intel roadmap. There was this Skymont architecture that was supposed to follow Skylake. But instead came Sunny Cove and the Skymont name was recycled. Not attached to the new E core architecture.

Was it really clear lead though?? I thought they were fairly close, and Intel had a clock speed advantage.
Shortly thereafter I think Rocket Lake was faster in single thread benchmarks, but the lead didn't transfer to gaming.

Desktop ST & gaming performance were pretty much on par actually. Not so in MT (due to larger core size and hence lesser cores; only 8 on top SKU, down from 10). But Rocket Lake was the world's worst in power efficiency. It not only ran super hot, but also guzzled way too much power & pretty much required a portable nuclear reactor to power the cpu. It was a disgrace. A product that should have never existed ever.

I hope tsmc n3b can clock just as high as intel 7 ultra..

I think the industry in general is moving away from very high clocked processors. Does N3B even have UHP libraries? I'm not sure.

 

[SiliconFly]

Tiger Lake vs Zen 3 mobile performance



They were on par. But Zen 3 mobile had more efficiency.

 

[SiliconFly]

Yeah zen 3 generation was good for amd.. clock speed will be a factor on who wins in single core between zen vs arrow lake

I hope it doesn't come to just clock speeds anymore. I think the future belongs to the company that can bring in huge architectural IPC improvements clock-for-clock, rather than high-clocked power-inefficient processors.