Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Geddagod]

To my knowledge ES2 don't have a real CPU ID, only the 0000 generic. On Sisoft there are ES2 samples with 0000. There is a Beta between ES2 and QS in the Arrow Lake roadmap, maybe it's a beta version? It's the third stepping on intel-gfx-ci.01.org, it could make sense. This is from the outdated ARL roadmap:

ES1/Alpha ww48'22
ES2 ww05'23
Beta ww09'23
QS ww27'23
PC/PV/PRQ ww31-33'23
RTS ww42'23

For ADL IIRC we saw QS chips (on sale on Ebay lol) ~3 months before launch. If QS chips don't start appearing in a month... then ye idk about how well MTL is doing...

 

[Doug S]

You can thank Keller for this, first and foremost. He gave the design teams what they wanted after years of being at the fabs mercy - the ability to do what's best for themselves. And for that, the logic was simple. N3 is a better node than Intel 3, and they needed whatever edge they could get. If the Lion Cove design team had more resources, perhaps they would do Intel 3, TSMC N3, and Intel 20A, but 3 entirely different nodes within a year's timespan is just too much.

Even if Intel 3 was a little bit better than TSMC N3 it might make sense for them from a competitive standpoint to use TSMC N3, as a way of limiting the number of N3 wafers AMD can get in the near term (i.e. until TSMC expands production capacity sufficiently that N3 wafers aren't limited for everyone who isn't Apple)

 

[Exist50]

To my knowledge ES2 don't have a real CPU ID, only the 0000 generic. On Sisoft there are ES2 samples with 0000.

It's possible there's a correlation but the two aren't strictly linked. Or perhaps more likely, Intel has internal QS candidates but isn't ready to actually declare that milestone and send them to OEMs yet.

Even if Intel 3 was a little bit better than TSMC N3 it might make sense for them from a competitive standpoint to use TSMC N3, as a way of limiting the number of N3 wafers AMD can get in the near term

TSMC isn't going to harm their relationship with AMD for Intel of all companies. No, if Intel 3 was truly competitive vs N3, Intel either wouldn't be using N3 at all, or would throw it all at graphics or similar.

 

[H433x0n]

No, if Intel 3 was truly competitive vs N3, Intel either wouldn't be using N3 at all, or would throw it all at graphics or similar.

N3 is the smallest generational improvement over the previous node, the first time they haven't improved sram density and the first time they've missed their public roadmap since they transitioned to FinFet. That's not me saying that - that's TSMC's public communications.

 

[eek2121]

Bob Swan bought a lot of TSMC silicon in 2021, a big portion of that is N3 allocation. I doubt Intel can go to TSMC and request a refund at this point.

Where else are you going to use those wafers? The product line that makes the most sense is client desktop. Mobile ARL has the most stringent efficiency requirements. Mobile is also the most ideal platform to derisk 20A node in preparation for 18A since it's a relatively small die size and the limited scope of 20A being a 'half' node works in this scenario. Server isn't an option due to the volume and greater efficiency requirements than client desktop.

You guys really don’t understand just how many units Intel ships. The allocation, if even accurate. would have to cover every single Intel part with a an integrated GPU, which means all of arrow lake + dedicated graphics.

Intel sells far more chips than AMD.

If Arrow Lake chips (p+e, outside of this SoC rumor) are fabbed at TSMC I will be completely shocked. I don’t believe it for a second.

As another has mentioned, their roadmap is essentially unchanged for at least 1.5-2 years with the exception of the drop of a Raptor Lake refresh and moving up the timelines on 20a/18a.

Further, Arrow Lake was designed and optimized around Intel 20A/18A. For them to move to an external fab, they would have had to have started before the original roadmap was given out! I don’t buy it, but we will see.

 

[Joe NYC]

You guys really don’t understand just how many units Intel ships. The allocation, if even accurate. would have to cover every single Intel part with a an integrated GPU, which means all of arrow lake + dedicated graphics.

Intel sells far more chips than AMD.

If Arrow Lake chips (p+e, outside of this SoC rumor) are fabbed at TSMC I will be completely shocked. I don’t believe it for a second.

As another has mentioned, their roadmap is essentially unchanged for at least 1.5-2 years with the exception of the drop of a Raptor Lake refresh and moving up the timelines on 20a/18a.

Further, Arrow Lake was designed and optimized around Intel 20A/18A. For them to move to an external fab, they would have had to have started before the original roadmap was given out! I don’t buy it, but we will see.

If Intel is incurring underutilization charges now, when all of the client and server CPUs are fabbed in Intel fabs, what is going to happen when the entire Arrow Lake and 2/3 of Meteor Lake are manufactured by TSMC?

 

[Doug S]

TSMC isn't going to harm their relationship with AMD for Intel of all companies. No, if Intel 3 was truly competitive vs N3, Intel either wouldn't be using N3 at all, or would throw it all at graphics or similar.

If Intel has a contract with TSMC to supply up to x number of wafers they have no choice but to provide them if Intel wants them, and from the talk a couple years ago it sounds like Intel negotiated such a contract. Maybe even partially prepaid for it.

The fact that may limit TSMC's ability to supply more wafers to AMD (at least until TSMC has had enough time to ramp up multiple N3 lines) is too bad for TSMC and AMD, but good for Intel. So even if Intel had a get-out clause in the deal where they could cancel the deal, they may have good reason not to exercise it even if Intel 3 was competitive with N3.

 

[Khato]

There certainly is some amusement to be had in Intel making use of a TSMC node for ARL core dice that's not exactly progressing as per plan. It'd be particularly amusing if the 20A variant is what ends up coming to market first, but unlikely.

As others have said, Intel making use of N3B goes back to whatever deal Swan made with TSMC. My impression is that Swan's (lack of) vision for Intel was to go fabless, and the design teams were all too happy to go along given the many years of manufacturing hamstringing. Most coverage implied that the deal included a pretty hefty sum of money being paid in advance, and while it would depend on the exact terms it's highly doubtful that any course of action other than making use of the purchased allocation would make any sense.

The real question is whether we're going to see any designs beyond ARL make use of TSMC for CPU core dice? That'd be an actual indicator of uncertainty in the manufacturing side going forward.

 

[coercitiv]

If Intel has a contract with TSMC to supply up to x number of wafers they have no choice but to provide them if Intel wants them, and from the talk a couple years ago it sounds like Intel negotiated such a contract. Maybe even partially prepaid for it.

The fact that may limit TSMC's ability to supply more wafers to AMD (at least until TSMC has had enough time to ramp up multiple N3 lines) is too bad for TSMC and AMD, but good for Intel.

So, according to you, Intel's big brain move was to secure a very large number of wafers that would indirectly prohibit TSMC from offering enough volume to other clients. This means they offered TSMC so much business that they essentially financed the R&D from their own pocket, potentially enabling TSMC to increase production plans. Such a massive volume would undoubtedly affect Intel's foundry business, robbing it of an essential stream of revenue. On top of this, Intel's margins will suffer since they're paying for vertical integration but they're not using it.

Meanwhile we see Intel scrambling to build new fabs all over the world, in a bid to compete with TSMC and stay relevant. While (allegedly) paying for new TSMC fabs.

 

[Geddagod]

So, according to you, Intel's big brain move was to secure a very large number of wafers that would indirectly prohibit TSMC from offering enough volume to other clients. This means they offered TSMC so much business that they essentially financed the R&D from their own pocket, potentially enabling TSMC to increase production plans. Such a massive volume would undoubtedly affect Intel's foundry business, robbing it of an essential stream of revenue. On top of this, Intel's margins will suffer since they're paying for vertical integration but they're not using it.

Meanwhile we see Intel scrambling to build new fabs all over the world, in a bid to compete with TSMC and stay relevant. While (allegedly) paying for new TSMC fabs.

ARL is going to use TSMC 3nm for something. That's not even the point of contention. Intel themselves made it clear. I'm not talking about leaks, but literal Intel information. Idk what to tell you. (Unless you think they use a samsung 3nm node lol).

I also see a lot of people talking about how much volume this would give TSMC. Well ye, it would but what choice did Intel have at the time? Their own future with their nodes were tremendously murky, and IIRC it wasn't until after Bob Swan reported that they were considering using external fabs that he then reported that they 'fixed' their Intel 7nm node. Which turned out to still be false, since Intel 4 isn't launching until the end of 2023, and even Intel claims they weren't 'HVM' ready with Intel 4 until the very end of 2022 I'm pretty sure.

Also the entire point of disaggregating the CPU was to reduce the size of the 'cutting edge' node die sizes - used for the CPU or GPU tiles. Assuming those thermal images of LNL were true, or even assuming that the size increase from a new arch is offset by using a +1 denser node and using MTL as a baseline, then an 8+16 ARL CPU tile would be ~90-120mm^2.
Those aren't exactly huge dies. Plus I doubt Intel is even going to be offering ARL to everyone and anyone, but just using them to fill in the premium segment. I also don't think desktop ships nearly as many units (or if not units total silicon area) as laptops+server do, both of which are claimed to use Intel's own nodes.

Ann Kellher had talked about how Intel had been giving the foundry team essentially an unlimited budget in fabs to get their nodes back on track. And lets not kid ourselves, Intel knows they won't be able to snag major customer wins until 18A at the earliest. Them using 3nm rather than Intel 20A is not going to have a major impact IMO other than in optics.

 

[Geddagod]

If Intel is incurring underutilization charges now, when all of the client and server CPUs are fabbed in Intel fabs, what is going to happen when the entire Arrow Lake and 2/3 of Meteor Lake are manufactured by TSMC?

They are?
I thought all the talk was that Intel is pumping out cheap ADL and RPL chips into the market to keep on utilizing their fabs, even if it meant decreasing margins and selling those chips at terrible prices (for them not for consumers lol).

 

[coercitiv]

ARL is going to use TSMC 3nm for something. That's not even the point of contention. Intel themselves made it clear. I'm not talking about leaks, but literal Intel information. Idk what to tell you. (Unless you think they use a samsung 3nm node lol).

My argument is Intel's decision of using N3 should not be seen as a gotcha move against AMD. Intel made this decision out of necessity, at considerable cost to their business as a whole. They probably did this to prevent greater harm, to secure access to a working leading edge node in a time of uncertainty.

 

[Geddagod]

You guys really don’t understand just how many units Intel ships. The allocation, if even accurate. would have to cover every single Intel part with a an integrated GPU, which means all of arrow lake + dedicated graphics.

Intel sells far more chips than AMD.

If Arrow Lake chips (p+e, outside of this SoC rumor) are fabbed at TSMC I will be completely shocked. I don’t believe it for a second.

As another has mentioned, their roadmap is essentially unchanged for at least 1.5-2 years with the exception of the drop of a Raptor Lake refresh and moving up the timelines on 20a/18a.

Further, Arrow Lake was designed and optimized around Intel 20A/18A. For them to move to an external fab, they would have had to have started before the original roadmap was given out! I don’t buy it, but we will see.

Even if LNC wasn't designed for an external fab, I strongly believe it was designed for Intel 3 in mind not Intel 20A.
When Ocean Cove got replaced with RWC, which is essentially just GLC+, the next step for Intel would have been a new architecture on the same (but slightly better) node- aka LNC on Intel 3.

Also AFAIK, architectures 'target' certain nodes, but it's not a hard requirement until ~3 years before launch when they start implementing the architecture into actual hard designs.

 

[A///]

scrambling is not the word I'd use. but will make some scrambled eggs in a few minutes.

 

[coercitiv]

scrambling is not the word I'd use. but will make some scrambled eggs in a few minutes.

Scramble

• To move or climb hurriedly, especially on the hands and knees.
• To struggle or contend frantically in order to get something.

Don't scramble too hard for those scrambled eggs!

 

[DrMrLordX]

Even if Intel 3 was a little bit better than TSMC N3 it might make sense for them from a competitive standpoint to use TSMC N3, as a way of limiting the number of N3 wafers AMD can get in the near term (i.e. until TSMC expands production capacity sufficiently that N3 wafers aren't limited for everyone who isn't Apple)

Intel paid TSMC up-front to build out additional N3 capacity. TSMC isn't taking capacity away from other customers to provide wafers to Intel.

So, according to you, Intel's big brain move was to secure a very large number of wafers that would indirectly prohibit TSMC from offering enough volume to other clients. This means they offered TSMC so much business that they essentially financed the R&D from their own pocket, potentially enabling TSMC to increase production plans. Such a massive volume would undoubtedly affect Intel's foundry business, robbing it of an essential stream of revenue. On top of this, Intel's margins will suffer since they're paying for vertical integration but they're not using it.

Meanwhile we see Intel scrambling to build new fabs all over the world, in a bid to compete with TSMC and stay relevant. While (allegedly) paying for new TSMC fabs.

Intel did finance TSMC's facility development by paying them billions of dollars for N3 capacity. Which is why it was so obnoxious of them to push the CHIPs act so hard later. Pretty sure it's confirmed that Intel did order N3 and pay up-front for the capacity, so we probably shouldn't brand it as an allegation at this point.

Granted there may be some hiccups with delivery of N3 to Intel, and there are numerous rumours regarding Intel deferring delivery of wafers (and of Apple taking more N3 wafers than expected). But these rumours are just that.

 

[A///]

Scramble

• To move or climb hurriedly, especially on the hands and knees.
• To struggle or contend frantically in order to get something.

Don't scramble too hard for those scrambled eggs!

Intel has always either expanded or retooled. intel isn't going to sit around moving at a snail's pace. I don't get some of you people. intel moves slow you whinge, intel moves fast you whinge, pat says silly you lot whinge.

some of you, not you specifically, seem content with intel putting a proverbial gun to their head and pulling the trigger and relying on amd to pick up the remnants and go on forward. the hyper focused posts on intel paying and using tsmc when they've used them for other things in the past is getting tiring. it probably cost intel less to buy fab space from tsmc than rush their own similar node, in which you lot would still whinge about.

no satisfying any of you it seems.

 

[coercitiv]

I don't get some of you people.

[snip]

no satisfying any of you it seems.

I don't get you specifically. You pick one verb in my reply and decide it's the exponent of some ideology forming among the forum members. It's just a verb, and it doesn't even have a negative meaning. (unless you're really bad at making scrambled eggs)

I'm not the one who unilaterally decided Intel is in a rush to compete with TSMC on a global scale. They said that, from the rooftops. They lobbied US and EU officials, asking for billions of dollars to make more and more foundries. In my view the verb "scramble" perfectly depicts Intel's actions, as they are in a race against time to match TSMC in both quality and volume.

If you're getting tired of people saying Intel is doomed, talk to those people, not me. I for one specifically refrained from commenting on imminent success or failure at Intel, and instead only addressed a specific claim regarding wafer allocation.

 

[Doug S]

So, according to you, Intel's big brain move was to secure a very large number of wafers that would indirectly prohibit TSMC from offering enough volume to other clients. This means they offered TSMC so much business that they essentially financed the R&D from their own pocket, potentially enabling TSMC to increase production plans. Such a massive volume would undoubtedly affect Intel's foundry business, robbing it of an essential stream of revenue. On top of this, Intel's margins will suffer since they're paying for vertical integration but they're not using it.

Meanwhile we see Intel scrambling to build new fabs all over the world, in a bid to compete with TSMC and stay relevant. While (allegedly) paying for new TSMC fabs.

No, Intel signed up for that capacity under previous leadership, when it wasn't clear how long it would take them to get out from under their process difficulties, and what sort of investment they'd be making for fabs in the future.

Once they had committed to it, the only question is what they would use it for, or whether they would try to get out from that commitment (which may have had negative financial consequences depending on the exact terms of their deal with TSMC)

Remember the original argument was "why would Intel use N3 if Intel 3 is supposedly better?" So the answer could be "Intel 3 is not better" or "Intel 3 won't be ready at the required volumes", or "it would cost Intel too much money to not use it" (in either penalties or sunk cost of prepayments) I was just saying there's another possible reason - i.e. even if they would be able to get out of their deal with TSMC with little financial impact that would leave TSMC with a lot of unused capacity that AMD might then use - "hey TSMC, looks like you have a lot of wafer starts going unused, how about we make a deal where we get an attractive price and you get revenue on what would otherwise be unused capacity" and use those cheaper chips to flood the market and frustrate Intel's attempts to return to profitability.

 

[Joe NYC]

They are?
I thought all the talk was that Intel is pumping out cheap ADL and RPL chips into the market to keep on utilizing their fabs, even if it meant decreasing margins and selling those chips at terrible prices (for them not for consumers lol).

That's what Intel did in Q4 2022. Stuffed the channel to the brink.

Which reduced the shipments in Q1 2023 and contributed underutilization charges starting to appear on financial statements in Q1 2023.

 

[igor_kavinski]

Can't Intel sell their N3 capacity to someone else, if suppose, Intel 3 is a resounding success and they don't have much need for N3? Or maybe they will use N3 for the non-K/mobile CPUs due to better power efficiency and use Intel 3 for their space heaters.

 

[Exist50]

In 2021 Intel Accelerated, Sanjay clarified that Intel 3 with PowerVia is prepared as backup plan of Intel 20A.
So, IMO, Lion Cove could be made by Intel 3 (with PowerVia).

Regarding "Intel 4/3 with PowerVia" thing, they intended it to be a real node, but the PnP/timeline/risk didn't align with any internal customer, so it was demoted to a "test node" or however they're spinning it.

Even if LNC wasn't designed for an external fab, I strongly believe it was designed for Intel 3 in mind not Intel 20A.
When Ocean Cove got replaced with RWC, which is essentially just GLC+, the next step for Intel would have been a new architecture on the same (but slightly better) node- aka LNC on Intel 3.

It's worth remembering that Lion Cove was originally planned for 2023. So the most likely candidates available were Intel 3 and N3. N3 seems to have been the higher priority one through the development process.

 

[igor_kavinski]

It's worth remembering that Lion Cove was originally planned for 2023.

And now we have to make do with a very possibly lame refresh. The life of techies sucks!

 

[eek2121]

Can't Intel sell their N3 capacity to someone else, if suppose, Intel 3 is a resounding success and they don't have much need for N3? Or maybe they will use N3 for the non-K/mobile CPUs due to better power efficiency and use Intel 3 for their space heaters.

They don’t need to.

GPUs, AI accelerators, IO, and dGPUs will all be at TSMC, regardless of the accuracy of that rumor (about Intel buying up 3nm), Intel will use everything even without the compute tiles.

That may very well be why they appear to be going ham with GPU performance improvements going forward: they have ample capacity.

 

[Joe NYC]

They are?
I thought all the talk was that Intel is pumping out cheap ADL and RPL chips into the market to keep on utilizing their fabs, even if it meant decreasing margins and selling those chips at terrible prices (for them not for consumers lol).

Notice "Excess Capacity Charges" on Intel quarterly reporting for Q1 2023. Below slide is for Client, and Intel's Datacenter also has the "Excess Capacity Charges"