Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[CouncilorIrissa]

Well you should remove L2 and see cause Snapdragon and M4 are using shared L2.

That's what I said about core-private caches? Apple's P-cores core-private cache is L1 and is included in the area, L2 excluded. For LNC it's L1 + L1.5 + L2 included.

 

[511]

That's what I said about core-private caches? P-cores core-private cache is L1 and is included in the area, L2 excluded. For LNC it's L1 + L1.5 + L2 included.

From Lion Cove as well
This is unfair comparison we had a better comparison here

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[CouncilorIrissa]

From Lion Cove as well
This is unfair comparison we had a better comparison here

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Why would I exclude L2? It's a core-private cache.

 

[511]

Why would I exclude L2? It's a core-private cache.

Core+L2 is the worst comparison of core sizes

These shared L2 will be used fully when you calculate core Performance and when calculating area you are excluding them. You need to take the least common denominator to compare cores.

 

[CouncilorIrissa]

Core+L2 is the worst comparison of core sizes

These shared L2 will be used fully when you calculate core Performance and when calculating area you are excluding them. You need to take the least common denominator to compare cores.

Following your logic we would need to add Intel's L3 to the core area then, because it's also a shared cache.

 

[511]

Following your logic we would need to add Intel's L3 to the core area then, because it's also a shared cache.

Least common denominator meaning only up to Core+L1

 

[CouncilorIrissa]

Least common denominator meaning only up to Core+L1

So what you're saying is that we should arbitrarily discard certain parts of the core from the calculation because Intel needs three levels of cache as opposed to Apple's one?

 

[511]

So what you're saying is that we should arbitrarily discard certain parts of the core from the calculation because Intel needs three levels of cache as opposed to Apple's one?

Really? if you count correctly except the new L0 cache it's pretty much same
L1/L2/L3 for all the vendors.

If you want a fair comparison you need to have the most common part between cores to compare and that is only Core+L1 between these cores.

 

[CouncilorIrissa]

Really? if you count correctly except the new L0 cache it's pretty much same
L1/L2/L3 for all the vendors.

If you want a fair comparison you need to have the most common part between cores to compare and that is only Core+L1 between these cores.

The L0 cache isn't "new", it's just a marketing gimmick. It really is just a renamed L1. Same capacity, similar bandwidth, standard 4 cycle latency for L1. (in fact Oryon has a 3-cycle L1i, except it's 192KB in size, and a 96KB L1D. Just like Apple used to prior to M3), it's just that prior to LNC Intel were behind everyone else with a 5-cycle L1.

There is no perfect comparison because memory subsystems are different, but a comparison that selectively excludes core-private resources from one core's area while factoring them in for another one is anything but fair.

 

[Doug S]

Well you should remove L2 and see cause Snapdragon and M4 are using shared L2.

I agree, just because Intel and Apple made different decisions about whether L2 should be private or shared in a cluster shouldn't bias the measurements.

However just eyeballing it, given that there are two L2 blocks and four P cores the fact the L2 block is smaller than a P core means a 3 mm^2 M4 P core plus its 25% share of L2 is less than 4.5 mm^2 and thus a little smaller than LNC's 4.6 mm^2 P core including its private L2.

 

[CouncilorIrissa]

I agree, just because Intel and Apple made different decisions about whether L2 should be private or shared in a cluster shouldn't bias the measurements.

However just eyeballing it, given that there are two L2 blocks and four P cores the fact the L2 block is smaller than a P core means a 3 mm^2 M4 P core plus its 25% share of L2 is less than 4.5 mm^2 and thus a little smaller than LNC's 4.6 mm^2 P core including its private L2.

At the end of the day, even with 1/4 of a L2 slice the core is anything but huge, which seems to be the myth perpetuated by many when it comes to the topic.

 

[igor_kavinski]

Panther Lake slides should be AI generated now?

Whoopee?

 

[Io Magnesso]

Damn. The only reference point is Skylake + L2 256KB - 217 million transistors and CypressCove(SunnyCove) + L2 512KB - 300 million transistors.

At the conference presentations on Intel's past manufacturing processes You may be using SRAM for testing.
It may be possible to use it to derive it...
To be honest, it's quite difficult...

 

[Io Magnesso]

No? Accouting for core-private caches only, M4's P-core is at ~3mm^2 and LNC is at 4.6mm^2.
View attachment 126085

I don't know where this myth of enormous Apple's cores comes from. They have large structures and they extract great perf/w from them, but they're not that large in terms of area. They're just *that good*.

I agree, but...
Considering the manufacturing process and the cell library used I don't know what will happen...

 

[Io Magnesso]

Panther Lake slides should be AI generated now?

Whoopee?

The slide font has changed from CES...
I really liked the previous font...

 

[Io Magnesso]

I agree, just because Intel and Apple made different decisions about whether L2 should be private or shared in a cluster shouldn't bias the measurements.

However just eyeballing it, given that there are two L2 blocks and four P cores the fact the L2 block is smaller than a P core means a 3 mm^2 M4 P core plus its 25% share of L2 is less than 4.5 mm^2 and thus a little smaller than LNC's 4.6 mm^2 P core including its private L2.

I agree too
The cash structure varies from manufacturer to manufacturer, and even if it is made by the same manufacturer, it depends on the type and application of the processor.

 

[Doug S]

At the end of the day, even with 1/4 of a L2 slice the core is anything but huge, which seems to be the myth perpetuated by many when it comes to the topic.

I think those myths arise because some want to deny Apple credit for its accomplishments. So Apple's CPUs are only able to do what they do because they use really big cores, or use more advanced processes, or use faster RAM, etc. etc. The goalposts are always moving so even when they aren't ahead by a process generation or aren't the only one using LPDDR in a PC there's always another excuse at the ready.

The reality is there's not anything Apple is doing that isn't available to companies with the resources of an AMD, an Intel, a Qualcomm, or a Samsung. They don't always make the same choices but they COULD and chose not to. The same is true in reverse of course, in areas where Apple is not the one in the lead (like GPU performance) there isn't anything the others are doing that Apple couldn't be doing.

 

[poke01]

I think those myths arise because some want to deny Apple credit for its accomplishments. So Apple's CPUs are only able to do what they do because they use really big cores, or use more advanced processes, or use faster RAM, etc. etc. The goalposts are always moving so even when they aren't ahead by a process generation or aren't the only one using LPDDR in a PC there's always another excuse at the ready.

The reality is there's not anything Apple is doing that isn't available to companies with the resources of an AMD, an Intel, a Qualcomm, or a Samsung. They don't always make the same choices but they COULD and chose not to. The same is true in reverse of course, in areas where Apple is not the one in the lead (like GPU performance) there isn't anything the others are doing that Apple couldn't be doing.

It’s simple really, when a lifestyle focused company outclasses an engineering focused one, people tend to make excuses.

 

[adroc_thurston]

when a lifestyle focused company outclasses an engineering focused one

Apple is neither, they're supply chain guys.

 

[511]

Apple is neither, they're supply chain guys.

Well they don't do anything except outsourcing all manufacturing 🤣

 

[S'renne]

Well they don't do anything except outsourcing all manufacturing 🤣

You do realise the Apple Silicon designs are all in house, not outsourced right?

 

[adroc_thurston]

You do realise the Apple Silicon designs are all in house, not outsourced right?

He means their actual device mfg is all Foxconn et al.
But that's also besides the point.

 

[Doug S]

It’s simple really, when a lifestyle focused company outclasses an engineering focused one, people tend to make excuses.

But that's just it, calling Apple a "lifestyle company" or "marketing company" etc. is another way to dismiss them, and deny that they have some of the best engineers in the world. Just because Tim Cook is basically the epitome of the nerdy supply chain focused MBA doesn't mean there isn't a LOT of value in being the BEST nerdy supply chain focused MBA there is. He avoids the negative side of the stereotype of having an MBA at the top because he didn't install a bunch of Tim Jrs underneath him and push out all the engineering and design focused managers. People look at Boeing and Intel and see what happens when you let MBAs take over and make decisions outside what should be their narrow silo.

Tim Cook sticks to what he knows - he knows how to make the business processes efficient, and he knows how to recognize and hire talented people. In other areas he trusts the people under him. For all the negatives Steve Jobs had that in common with Tim Cook. He recognized talent in other people, and stuck to what he knows too. They may have differed a bit in their approach to personal management and motivation, however

This is why the argument some make that you have to have an engineer in charge of an Intel or a Boeing, as if that will sort out all their problems, is flawed. Most engineers make terrible managers. If Intel replaced their management structure with a bunch of engineers they'd probably be well on their way to bankruptcy, because you have to have some people who know the business side to do demand forecasts for the fab business, plan optimal tax strategies for the long term investments in new fabs, decide if and when to enter new market segments or exit ones that aren't performing well etc. Having an Intel that's managed solely by engineers would be as bad of an idea as having one that's managed solely by MBAs. You need both, but they need to stick to their respective roles - and you need a CEO who enforces that. Apple shows how that can work.

 

[511]

I agree, just because Intel and Apple made different decisions about whether L2 should be private or shared in a cluster shouldn't bias the measurements.

Yeah

However just eyeballing it, given that there are two L2 blocks and four P cores the fact the L2 block is smaller than a P core means a 3 mm^2 M4 P core plus its 25% share of L2 is less than 4.5 mm^2 and thus a little smaller than LNC's 4.6 mm^2 P core including its private L2.

The thing with shared L2 is you can have the entire L2 to yourself for 1 active core so M4 core can use the entire 8MB L2.
If we compare only the core structure Lion Cove is bigger than M3/M4 without any noticable advantage except wider SIMD Units.
I also said that Intel messed up the LNC Design.

 

[MS_AT]

The reality is there's not anything Apple is doing that isn't available to companies with the resources of an AMD, an Intel, a Qualcomm, or a Samsung. They don't always make the same choices but they COULD and chose not to. The same is true in reverse of course, in areas where Apple is not the one in the lead (like GPU performance) there isn't anything the others are doing that Apple couldn't be doing.

Not that I disagree but what about patent laws?

The thing with shared L2 is you can have the entire L2 to yourself for 1 active core

Isn't it the same same with L3? Of course it would be also important to tell victim caches from regular ones when streaming workloads are evaluated. What about SLC?