Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

If Intel can't stop the bleeding of market share in the high margin DC with CWF, they are in trouble. My question is, will 288 cores of Skymont be enough to combat 192 cores on Turin Dense?

Should be enough cause the architecture is not a power hog and has better PPA tham zen at lower power levels like their P cores

 

[511]

What is #1 based on? Not denying, just curious about the numbers.

TSMC N3B node and Advance packing N6 is cheap though and in their calls they said the same thing lower margin due to external foundry

 

[DavidC1]

Should be enough cause the architecture is not a power hog and has better PPA tham zen at lower power levels like their P cores

We'll see how the Sierra Forest AP does first.

 

[511]

We'll see how the Sierra Forest AP does first.

Sure we already have the SP version

 

[DavidC1]

If Intel can't stop the bleeding of market share in the high margin DC with CWF, they are in trouble. My question is, will 288 cores of Skymont be enough to combat 192 cores on Turin Dense?

Theoretically, Clearwater Forest is a tour de force. I say theoretically, because Granite Rapids is suffering from scaling issues. It's rushed just like Arrowlake is. Intel says Arrowlake's performance issues can be mitigated, I don't know if that's true for Granite Rapids. 20% difference in MT would have been good. It's 40% in 2P. Unfortunately due to that the situation has not improved substantially over when they got Emerald Rapids.

Sierra Forest seems to have little bit of scaling issues too. Can't tell if that's tile immaturity or something to do with the Birch Stream platform. Remember CWF uses same socket as Sierra.

Again, since Skymont is essentially Zen 5c in Integer performance per clock, and in FP it's much closer. 288 cores is more than enough to make up for lack of SMT over a 192 core SMT enabled one. This is a theoretically very viable approach. Actually in some cases it is advantageous, because the total amount of threads are less.

As a product? It depends on how much the base Foveros cache layer will help with scaling that many cores. It depends on many minor details we don't know. How is the fabric? How does the memory controller scale? Bandwidth and latency of all the parts.

If it does well it won't just threaten Turin, but their own P core Xeon.

 

[511]

As a product? It depends on how much the base Foveros cache layer will help with scaling that many cores. It depends on many minor details we don't know. How is the fabric? How does the memory controller scale? Bandwidth and latency of all the parts.

If it does well it won't just threaten Turin, but their own P core Xeon.

Which is a good thing cause the P cores are soo bad now in PPA

 

[DrMrLordX]

Ya. The hell they did. Pls check the posts.

I repeat: 9800X3D and Turin. Are you getting it yet?

When a person tries to paint it as a Intel specific problem, it's important to demystify.

It is an Intel-specific problem!

 

[511]

I repeat: 9800X3D and Turin. Are you getting it yet?

No argument turin is good same with X3D

It is an Intel-specific problem!

These OS/BIOS issue are not Intel specific problem AMD had it with Zen5 as well

 

[DrMrLordX]

These OS/BIOS issue are not Intel specific problem AMD had it with Zen5 as well

Turin didn't, 9800X3D didn't . . . and the people that actually wanted vanilla Granite Ridge for productivity didn't even notice because it did not affect them.

Meanwhile, in Intel land, things are quite different.

 

[511]

Turin didn't, 9800X3D didn't . . . and the people that actually wanted vanilla Granite Ridge for productivity didn't even notice because it did not affect them.

Meanwhile, in Intel land, things are quite different.

Let them release the patch before we conclude if it was productivity that was hit or games or it is the hardware that has flaws 🙂 after that i can conclude

 

[OneEng2]

What is #1 based on? Not denying, just curious about the numbers.

As for #2 I'm not sure DC make or breaks the desktop?

#1 is my strong "guess" and is based on the idea that as long as share prices are high (based on the promise of 18A and future products), it is expensive to purchase Intel .... and risky. Buy now and things go south and you eat billions upon billions of dollars loss on your investment (ie, Twitter).

Should be enough cause the architecture is not a power hog and has better PPA tham zen at lower power levels like their P cores

Yes, but not power per core and certainly not in MT. Per core licensing would make a Zen 5 solution highly preferable to a 288 core Skymont solution due to licensing costs.

Theoretically, Clearwater Forest is a tour de force. I say theoretically, because Granite Rapids is suffering from scaling issues. It's rushed just like Arrowlake is. Intel says Arrowlake's performance issues can be mitigated, I don't know if that's true for Granite Rapids. 20% difference in MT would have been good. It's 40% in 2P. Unfortunately due to that the situation has not improved substantially over when they got Emerald Rapids.

Sierra Forest seems to have little bit of scaling issues too. Can't tell if that's tile immaturity or something to do with the Birch Stream platform. Remember CWF uses same socket as Sierra.

Again, since Skymont is essentially Zen 5c in Integer performance per clock, and in FP it's much closer. 288 cores is more than enough to make up for lack of SMT over a 192 core SMT enabled one. This is a theoretically very viable approach. Actually in some cases it is advantageous, because the total amount of threads are less.

As a product? It depends on how much the base Foveros cache layer will help with scaling that many cores. It depends on many minor details we don't know. How is the fabric? How does the memory controller scale? Bandwidth and latency of all the parts.

If it does well it won't just threaten Turin, but their own P core Xeon.

Core per core, I can't see Skymont being anywhere near Zen 5c in DC workloads. It lacks SMT and AVX512. In fact, I could see Zen 5c being anywhere from 40% to 60% higher performance per core than Skymont in DC workloads.

So lets first look at just overall performance of a 192 core Zen 5c vs a 288 core Skymont under these assumptions. Skymont has 50% more cores, but Zen 5c performs 50% better per core .... so an even race but.......

Now look at it from a licensing standpoint. Skymont has 50% more cores and from an annual license costs 50% more per year to operate than Zen 5c.

Lots of assumptions here for sure, I just point out that Clearwater forest isn't necessarily a slam dunk for Intel.

 

[Hulk]

Is it likely that until put more resources into the development of skymont because it does double duty, client and server? Whereas lion cove is pretty much just client.

 

[511]

Core per core, I can't see Skymont being anywhere near Zen 5c in DC workloads. It lacks SMT and AVX512. In fact, I could see Zen 5c being anywhere from 40% to 60% higher performance per core than Skymont in DC workloads.

How are you calculating per core performance is AVX-512 included in them than yes elso no for pure integer workloads which many are both will be similar integer performance per thread

So lets first look at just overall performance of a 192 core Zen 5c vs a 288 core Skymont under these assumptions. Skymont has 50% more cores, but Zen 5c performs 50% better per core .... so an even race but.......

Now look at it from a licensing standpoint. Skymont has 50% more cores and from an annual license costs 50% more per year to operate than Zen 5c.

Lots of assumptions here for sure, I just point out that Clearwater forest isn't necessarily a slam dunk for Intel.

I agree for VM part but there are customers who disables SMT so it will give them more physical cores to work with
On a sidenote not a single site benchmarks the accelerator in Silicons they are niche but have decent use cases

 

[cannedlake240]

In fact, I could see Zen 5c being anywhere from 40% to 60% higher performance per core than Skymont in DC workloads

Yeah, idk about that... Unless 18A is complete garbage(which is a possibility) 40-60% higher perf seems too optimistic outside niche HPC/AI workloads and Clearwater has more cores. Epyc Zen 4C had 50% higher perf per core... Against 8ch Sierra that had Crestmont and 100mb L3. CLF has Darkmont equipped with more L3 and likely faster 12ch DDR5. Crestmont was slower than Zen 4 in int perf let alone FP, but Skymont already narrowed that gap

 

[SiliconFly]

.

 

[ondma]

Oh yeah! X3D didn’t. Turin didn’t. Same as GNR didn’t. And Lunar Lake didn’t.

When Zen 5 desktop parts were launched it was a disaster requiring some agesa bios updates and windows 24H2 patches. Same like ARL now requires similar bios updates & possible windows patches.


Looks like some have either forgotten about it already or just want to ignore it.


Apparently, it was okay to wait for amd’s patches, but not now for Intel’s.

Well, with the exception of the x3D parts, Zen 5 is still a pretty mediocre release. They jury is still out on ARL, but I dont really expect some bios updates to sufficiently improve the horribly inconsistent gaming performance to make it competitive with current Zen 5 or previous x3D parts, much less 9000 x3D. There seems to just be something fundamentally wrong with ARL for gaming.

 

[igor_kavinski]

There seems to just be something fundamentally wrong with ARL for gaming.

This is what's probably wrong:



I suppose they made this weird core layout in Arrow Lake to reduce the context switch latency as the threads jump from E-cores to P-cores during periods of high compute demand but Windows scheduler or GPU drivers or even game engines were not ready for such a radical change.

 

[LightningZ71]

Yeah, idk about that... Unless 18A is complete garbage(which is a possibility) 40-60% higher perf seems too optimistic outside niche HPC/AI workloads and Clearwater has more cores. Epyc Zen 4C had 50% higher perf per core... Against 8ch Sierra that had Crestmont and 100mb L3. CLF has Darkmont equipped with more L3 and likely faster 12ch DDR5. Crestmont was slower than Zen 4 in int perf let alone FP, but Skymont already narrowed that gap

My biggest concern for Intel's very high core count 'mont server processors has nothing to do with the cores themselves, save if they can have a competitive AVX-512 implementation and remain compact and efficient enough, but is far more about Intel's mesh fabric connecting them all. 288 cores in clusters of 4 is still 72 reservation stations. How will the mesh affect performance for them?

 

[tsamolotoff]

I suppose they made this weird core layout in Arrow Lake to reduce the context switch latency as the threads jump from E-cores to P-cores during periods of high compute demand but Windows scheduler or GPU drivers or even game engines were not ready for such a radical change.

In ring bus, every core is equal and latency does not depend on physical distance - data has to travel whole ring before any read/write happens

 

[cannedlake240]

My biggest concern for Intel's very high core count 'mont server processors has nothing to do with the cores themselves, save if they can have a competitive AVX-512 implementation and remain compact and efficient enough, but is far more about Intel's mesh fabric connecting them all. 288 cores in clusters of 4 is still 72 reservation stations. How will the mesh affect performance for them?

It'll definitely affect memory and LLC latency same way it's on Granite rapids, but a larger local base tile cache and SNC3 mode probably compensate for that

 

[Markfw]

Oh yeah! X3D didn’t. Turin didn’t. Same as GNR didn’t. And Lunar Lake didn’t.

When Zen 5 desktop parts were launched it was a disaster requiring some agesa bios updates and windows 24H2 patches. Same like ARL now requires similar bios updates & possible windows patches.


Looks like some have either forgotten about it already or just want to ignore it.


Apparently, it was okay to wait for amd’s patches, but not now for Intel’s.

I don't know how you can justify saying Zen 5 at launch was a disaster. I was one of the first to buy Zen 5, and I have not updated bios or updated the OS or even BOOTED THE COMPUTER since it was new, and no issues months later.

This may be an Intel thread but at least you don't need to lie like crazy about AMD.

 

[Hulk]

This is what's probably wrong:

View attachment 111456

I suppose they made this weird core layout in Arrow Lake to reduce the context switch latency as the threads jump from E-cores to P-cores during periods of high compute demand but Windows scheduler or GPU drivers or even game engines were not ready for such a radical change.

Intel said that the change in the P/E core layout was to reduce heat concentrations in high loads "like gaming." Yes, they said it. Ironic, no?

 

[Hulk]

As I noted earlier Intel gave me two options for replacing my 14900K. Send mine in and they send the replacement about a week later.

Cross-ship but that will cost $25.

As someone here suggested I asked them that since is my 3rd defective part would they consider a refund or an Arrow Lake CPU replacement.

I'll let you all know how that turns out. Pretty sure they're going to say no and I'll have to resell the replacement and move to Zen or use the Raptor downclocked and bide my time.

 

[igor_kavinski]

use the Raptor downclocked and bide my time.

You could use the replacement normally since Intel says all kinks have been worked out. Could be a test to see how truthful Intel is being or if they are totally clueless about their own product.

 

[DavidC1]

288 cores in clusters of 4 is still 72 reservation stations. How will the mesh affect performance for them?

Also keep in mind the 288 core Clearwater Forest is 12 dies of 24 cores each, with 24 cores being composed of 6x quad core clusters.

Intel said that the change in the P/E core layout was to reduce heat concentrations in high loads "like gaming." Yes, they said it. Ironic, no?

Arrowlake was supposed to be before Lunarlake, so not only it's basically their first try it's also run into development problems, so we likely cannot pinpoint any high level problem as a single major fault.