Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[jdubs03]

So what? Apple cores operate at much lower clock speeds, are in a completely different software model (ARM) and do not offer high enough performance (if at all) to justify a mass switch of PCs to ARM processors. Most people don't know what IPC is, and for many it's about x86 and peak performance. IPC and architecture are only interesting to us (enthusiasts), for the rest of the people it doesn't really matter much.

Apple has made some inroads into Intels market share lead for laptops over the recent years. And the M4 Pro/Max should be a pretty solid package overall. The Max won’t be at 9950X/285K in MT for desktop-level performance (courtesy of its lower thread count), but it will sip power in comparison and smash the competition in ST at the same time. The Max in a laptop form factor might even match or come close to HX class performance (again at much less power).

 

[AMDK11]

Apple has made some inroads into Intels market share lead for laptops over the recent years. And the M4 Pro/Max should be a pretty solid package overall. The Max won’t be at 9950X/285K (and MT in desktop-level performance (courtesy of its lower thread count), but it will sip power in comparison and smash the competition in ST at the same time. The Max in a laptop form factor might even match or come close to HX class performance (again at much less power).

How much faster will it be in ST? I don't think this is a big enough vulnerability to justify moving from an entire x86-64 environment.

For me, ARM is just a curiosity that is nice to have and shows what can still be achieved in terms of computing core design and IPC achieved. But I'm not going to give up on x86 just for this reason, and x86 is growing and will continue to be in good shape despite temporary weaknesses/downtime.

Further development of x86S 1.2 and the introduction of APX instead of 16x GPR 64-bit, 32x GPR 64-bit will provide significant benefits.

"Intel® APX doubles the number of general-purpose registers (GPRs) from 16 to 32. This allows the compiler to keep more values in registers; as a result, APX-compiled code contains 10% fewer loads and more than 20% fewer stores than the same code compiled for an Intel® 64 baseline.2 Register accesses are not only faster, but they also consume significantly less dynamic power than complex load and store operations."

 

[SiliconFly]

.

 

[jdubs03]

How much faster will it be in ST? I don't think this is a big enough vulnerability to justify moving from an entire x86-64 environment.

The M4 series should be about 10 to 15% faster in outright single thread performance; based on the M4 clocking to 4.4GHz.

On a sidenote, I’m surprised that Apple doesn’t increase the clock speeds a little bit on the Pro and Max SKUs, seems like a way for further differentiation.

 

[cannedlake240]

RWC is a horrible nightmare

Then all of Intel's modern cores are? Redwood is literally just a node shrink of Golden cove. The reason it regressed a bit was due to abysmal uncore perf( ring clock <4ghz, high memory latency). Plus all x86 cores perform worse in mobile variants due to power reasons. Just look at Zen mobile vs Desktop, same with Zen 5. Lion cove is more complicated because it inherits the SoC from MTL

 

[AMDK11]

The M4 series should be about 10 to 15% faster in outright single thread performance; based on the M4 clocking to 4.4GHz.

On a sidenote, I’m surprised that Apple doesn’t increase the clock speeds a little bit on the Pro and Max SKUs, seems like a way for further differentiation.

Well, I don't know if the difference is big enough to be worth switching from x86 to ARM. As I wrote, there is no gap, and changing from x86 to ARM means a gap and giving up the entire environment that I, among others, care about.

 

[AMDK11]

Then all of Intel's modern cores are? Redwood is literally just a node shrink of Golden cove. The reason it regressed a bit was due to abysmal uncore perf( ring clock <4ghz, high memory latency). Plus all x86 cores perform worse in mobile variants due to power reasons. Just look at Zen mobile vs Desktop, same with Zen 5. Lion cove is more complicated because it inherits the SoC from MTL

RedwoodCove in GraniteRapids is something more because it includes an 8-Way decoder like LionCove and gives a gain of about +10% to IPC.

 

[cebri1]

RedwoodCove in GraniteRapids is something more because it includes an 8-Way decoder like LionCove and gives a gain of about +10% to IPC.

I believe a little bit less than that. Close to 6-7%, I think the new memory and the added cache are doing the heavy lifting. RWC+ is still GC++++. A notch behind Zen5 but not a whole generation behind. Not bad for a 3 year old arch with some tweaking.

 

[AMDK11]

I believe a little bit less than that. Close to 6-7%, I think the new memory and the added cache are doing the heavy lifting. RWC+ is still GC++++. A notch behind Zen5 but not a whole generation behind. Not bad for a 3 year old arch with some tweaking.

Intel officially acknowledges that GraniteRapids' RedwoodCove has an 8-wide decoder, which MeteorLake does not.

 

[poke01]

almost no one is switching because Apple is 15% faster in ST and has better perf/w, these benefit Apple and Mac users only.

Now unless Apple decides to sell its chips to others only then do they pose a real threat to Intel. For now Apple beating Intel is wrong in optics only.

 

[Hitman928]

Since Intel & AMD are using only 3-3 in their CPUs, there's something that needs to be pointed out.

What makes you think this?

 

[OneEng2]

Depends on metrics
density it is slightly behind but on PPW it is between N3E and N5 and the fin configuration as well you can check both of these it is between N4P and N3E also the 3-3 fin is similar between Intel 3 and N3E according to wikichip
All the sources are listed stop saying Intel 3 is at N5 level outside of density unless specifying the use case which in Terms of Intel and AMD is HPC

Intel 4 Deep Dive - Semiwiki

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12). “Intel 4 CMOS...

semiwiki.com

VLSI Technology Symposium – Intel describes i3 process, how does it measure up? - Semiwiki

At the VLSI Technology Symposium this week Intel released details on their i3 process. Over the last four nodes Intel has had an interesting process progression. In 2019, 10nm finally entered production with both high performance and high-density standard cells. 10nm went through several...

semiwiki.com

By TSMC own admission N3P is on Par with 18A
View attachment 108213

Yes all those years of 14nm++++ and 10nm+++
Are finally ending pat should get credit for correcting predecessors mistake

I have said it many time Intel's P core team is horrendously bad look at how efficient and cool and less power Sierra forest consumes it's not because of node but because P cores are disappointing

I think it will be 25-30% dependent on workloads

It's not crestmont but a buffed up chadmont so i don't think performance per core gap will be that much wider between 5C/ and Darkmont TSMC saying 18A matches N3P so how is it struggling considering N3P is the best Process in N3 family 🤣

Intel will have 2 differentiation Supply and good SW i don't believe AMDs supply even in server space otherwise with the massive lead they have they should have taken market share crazily which they didn't it will be even tougher now

If Intel makes the 18A process release on time they will be up against AMD on N3P ... true, but I am GUESSING that Intel will release Q4 2025 at the earliest. Samsung had a he** of a time with GAA. Yields I believe. I just find it hard to believe (and have since Intel came up with the crazy aggressive process roadmap slide) that Intel is going to pull off such a large number of changes into 18A. I guess I just lost faith after the afore mentioned 14++++++ and 10+++++ fiasco .

You may be right about the P core architecture. It seems like the perf/watt of the E cores is impressive in comparison. We will have to re-visit the performance guessing after release and see which one of us was closer .

TSMC N4P:
3-3 Fin -> 98 MTr/mm²
2-2 Fin -> 144 MTr/mm²

TSMC N3B:
3-3 Fin -> 124 MTr/mm²
2-2 Fin -> probably exceeds 180 MTr/mm²

Intel 3:
3-3 Fin -> 124 MTr/mm²
2-2 Fin -> 144 MTr/mm²

This ignores performance entirely, that's much harder to quantify.

So Intel 3 is roughly equivalent to N4P and below N3B. This is not different from what I have read other places.

So 2024 Turin will be on N4P and therefore be about process equivalent to Granite Rapids Intel 3. Since both designs utilize "P" core only technology, it will be interesting to see how power effective each design will be when placed in the context of being design power limited.

 

[AMDK11]

almost no one is switching because Apple is 15% faster in ST and has better perf/w, these benefit Apple and Mac users only.

Now unless Apple decides to sell its chips to others only then do they pose a real threat to Intel. For now Apple beating Intel is wrong in optics only.

This is not enough for such a radical change from x86 to ARM. If only it were 40-50% more but it isn't. I don't think over 90% of people would choose ARM (Apple Mx) just because it has a much higher IPC and an overall ST performance of +10-15%. Most people have no idea about core micro architecture and IPC. So true.

 

[OneEng2]

Of course, Turin D 192 core will be on N3E and provide both power and density improvements. But then, it won't be Intel P cores that this Turin will be up against (I don't believe).

 

[FlameTail]

TSMC N4P:
3-3 Fin -> 98 MTr/mm²
2-2 Fin -> 144 MTr/mm²

TSMC N3B:
3-3 Fin -> 124 MTr/mm²
2-2 Fin -> probably exceeds 180 MTr/mm²

Intel 3:
3-3 Fin -> 124 MTr/mm²
2-2 Fin -> 144 MTr/mm²

This ignores performance entirely, that's much harder to quantify.

Where are these density values from?

 

[cannedlake240]

RedwoodCove in GraniteRapids is something more because it includes an 8-Way decoder like LionCove and gives a gain of about +10% to IPC.

It's probably a typo or they're talking about uop cache

 

[cebri1]

Intel officially acknowledges that GraniteRapids' RedwoodCove has an 8-wide decoder, which MeteorLake does not.

Was that ever confirmed?

 

[AMDK11]

It's probably a typo or they're talking about uop cache

https://cdn.wccftech.com/wp-content/uploads/2024/05/2024-06-04_8-33-37-1456x910.jpg

 

[DavidC1]

Keep in mind when comparing Lion Cove to Zen 5 that Lion Cove is a mere expansion of what it was before and Zen 5 is a departure. Zen 5 is not only substantially smaller than Lion Cove, it has way more headroom for it in the future because it's a change in architecture. This is despite the Lion Cove being on N3B.

Without Skymont adding heaps, Arrowlake would have been a dud with all Lion Cove cores.

It might be "Lion" Cove, but it's more like a fat house cat.

 

[Josh128]

Of course, Turin D 192 core will be on N3E and provide both power and density improvements. But then, it won't be Intel P cores that this Turin will be up against (I don't believe).

Why not? That Zen 5C Turin is about to be announced in a couple of weeks, no?

 

[AMDK11]

Keep in mind when comparing Lion Cove to Zen 5 that Lion Cove is a mere expansion of what it was before and Zen 5 is a departure. Zen 5 is not only substantially smaller than Lion Cove, it has way more headroom for it in the future because it's a change in architecture. This is despite the Lion Cove being on N3B.

Without Skymont adding heaps, Arrowlake would have been a dud with all Lion Cove cores.

It might be "Lion" Cove, but it's more like a fat house cat.

LionCove is a departure from Intel's approach and philosophy from P6 to RedwoodCove. LionCove is a fundamental departure from previous generations of Cove and is now more Zen than ever.

From P6(Pentium PRO) to RedwoodCove, the schedule and execution ports were common to FP and ALU, i.e. FP-ALU. LionCove separates FP from ALU and implements separate/dedicated blocks with execution ports for FP and separate ones for ALU. If no one sees such a fundamental change, I don't know if anyone will ever notice any changes.

 

[DavidC1]

LionCove is a departure from Intel's approach and philosophy from P6 to RedwoodCove. LionCove is a fundamental departure from previous generations of Cove and is now more Zen than ever.

Lion Cove brings absolutely no new ideas, regresses from the predecessor of 3 years ago in some aspects, and is still way bigger than competition, despite having significant process advantage.

Putting a lipstick on a female pig doesn't make it an attractive woman.

 

[jdubs03]

Lion Cove brings absolutely no new ideas, regresses from the predecessor of 3 years ago in some aspects, and is still way bigger than competition, despite having significant process advantage.

Putting a lipstick on a female pig doesn't make it an attractive woman.

Unless you’re Kermit it does!

 

[cebri1]

https://cdn.wccftech.com/wp-content/uploads/2024/05/2024-06-04_8-33-37-1456x910.jpg

There is a non zero chance than Clearwater Forest will mop the floor with GNR in about 3Q.

 

[Dayman1225]

There is a non zero chance than Clearwater Forest will mop the floor with GNR in about 3Q.

Probably why Intel is is no rush to get another P core platform out before Diamond Rapids in H2’26