Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[511]

Too bad Intel botched ARL the IMC is crazy good in ARL

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[igor_kavinski]

This needs to supported by OS as well knowing windows see you in couple of years on Linux we should be fine.

Intel could always bribe M$. They did that before for Alder Lake's hybrid scheduling updates.

 

[511]

Intel could always bribe M$. They did that before for Alder Lake's hybrid scheduling updates.

Intel did not bribe they simply did the entire stuff on their own why do you think there were so less problems except for few DRM issues I don't think MSFT is even capable of that.

 

[igor_kavinski]

Intel did not bribe they simply did the entire stuff on their own why do you think there were so less problems except for few DRM issues I don't think MSFT is even capable of that.

I don't think M$ would let any external party near their source code. It's their proprietary secret sauce.

 

[511]

I don't think M$ would let any external party near their source code. It's their proprietary secret sauce.

Well if they won't allow that with AMD or Intel windows would be in a bad state there are specific work that Intel/AMD do that reaches MSFT

 

[MS_AT]

This needs to supported by OS as well knowing windows see you in couple of years on Linux we should be fine.

Out of curiosity in which areas Linux leads Windows support when it comes to Intel CPUs? For Alder Lake it was the other way around iirc, it took months for Linux to treat E cores properly. The one thing I recall was related to improper handling of Lunar Lake, at least Charlie was babbling about this and low CB24 scores.

I don't think M$ would let any external party near their source code. It's their proprietary secret sauce.

This is what NDAs are for. In business you build relationships on trust, and I am sure M$ trusts their formidable army of lawyers

 

[511]

Out of curiosity in which areas Linux leads Windows support when it comes to Intel CPUs? For Alder Lake it was the other way around iirc, it took months for Linux to treat E cores properly. The one thing I recall was related to improper handling of Lunar Lake, at least Charlie was babbling about this and low CB24 scores.

Scheduling in Linux the core handling is a tad bit better also the LNL thingy existed on Windows as well if the power profile was set to battery saver

 

[511]

https://twitter.com/x/status/1963948140748222527

 

[igor_kavinski]

Sucks that they couldn't put the new cores in Arrow Refresh. I mean, how hard could it have been? Just search and replace Lion Cove and Skymont with Cougar Cove and Darkmont in the design files, right?

RIGHT?????

 

[511]

Sucks that they couldn't put the new cores in Arrow Refresh. I mean, how hard could it have been? Just search and replace Lion Cove and Skymont with Cougar Cove and Darkmont in the design files, right?

RIGHT?????

You need a new mask new stepping for 8+16 Tile which would still suck due to the horrible uncore of ARL

 

[igor_kavinski]

You need a new mask new stepping for 8+16 Tile which would still suck due to the horrible uncore of ARL

All excuses. They could do it if they really wanted to. If Pat had been fired earlier.

 

[511]

All excuses. They could do it if they really wanted to. If Pat had been fired earlier.

Well now that he has been fired no one is resurrecting PTL-HX

 

[igor_kavinski]

Well now that he has been fired no one is resurrecting PTL-HX

He didn't leave money for doing that. Burned it on 18A.

 

[511]

He didn't leave money for doing that. Burned it on 18A.

PTL-HX was on 18A it doesn't exist anymore

 

[igor_kavinski]

PTL-HX was on 18A it doesn't exist anymore

Because 18A wasn't good enough in time for it. They should have put NO egg in the stupid 18A basket and bought more TSMC capacity. Use 18A for test chips and silly stuff like Bartlett Lake 12P shrink and Skymont only N405 netbook chip until yields improved enough to ditch TSMC. Idiots. And they get paid really well for making idiotic decisions.

 

[igor_kavinski]

By the way, the APX spec doc latest one is over 300 pages. No wonder they gonna rewrite code dynamically and inject into game executables for Nova Lake. It's their only hope of a win, at least in some high profile titles.

 

[Thunder 57]

By the way, the APX spec doc latest one is over 300 pages. No wonder they gonna rewrite code dynamically and inject into game executables for Nova Lake. It's their only hope of a win, at least in some high profile titles.

Despite what that clown says they are not going to do that. Having different executables floating around out there would be a nightmare. How much could they hope to optimize them anyway?

 

[511]

Despite what that clown says they are not going to do that. Having different executables floating around out there would be a nightmare. How much could they hope to optimize them anyway?

Sooner or later everyone has to do this just like we had x86 and x64 binaries but I don't think it will start as soon as NVL Launchea except for few games.

 

[Thunder 57]

Sooner or later everyone has to do this just like we had x86 and x64 binaries but I don't think it will start as soon as NVL Launchea except for few games.

There's a difference between compiling with 32 or 64 bit in mind (or APX someday) and tearing open a compiled file, "optimizing it" and re-compiling it. AV and anti-cheat would be all over it.

 

[511]

There's a difference between compiling with 32 or 64 bit in mind (or APX someday) and tearing open a compiled file, "optimizing it" and re-compiling it. AV and anti-cheat would be all over it.

i definitely don't believe the clown for that part but i can believe Intel Forcing some developers to use More Modern Instruction or compiling with APX/AVX10.2

 

[igor_kavinski]

AV and anti-cheat would be all over it.

Unless Intel also inserts some kind of crypto key in it to confirm authenticity and shares that information with AV/anti-cheat software authors. I know, it's a big ask but at this point, Intel may do anything to get back their edge. They went to the trouble of creating APO, remember? Instead of just admitting their stupid mistake that hybrid cores suck.

I bet before every hardware launch, in front of their software people they go, "Your mission, should you choose to accept it, is to cover up our hardware design teams' follies. Failure to do so may result in your jobs self combusting".

 

[MoistOintment]

Because 18A wasn't good enough in time for it. They should have put NO egg in the stupid 18A basket and bought more TSMC capacity. Use 18A for test chips and silly stuff like Bartlett Lake 12P shrink and Skymont only N405 netbook chip until yields improved enough to ditch TSMC. Idiots. And they get paid really well for making idiotic decisions.

Shrinking Bartlett Lake to 18A makes no sense. Its whole purpose is to cheaply utilize existing IP and spare Intel 7 production capacity for a NEX/Embedded product line. Shrinking to 18A defeats the entire purpose.

Sucks that they couldn't put the new cores in Arrow Refresh. I mean, how hard could it have been? Just search and replace Lion Cove and Skymont with Cougar Cove and Darkmont in the design files, right?

RIGHT?????

The *primary* difference between new cores and LNC is that they're on 18A. Any design changed is largely inconsequential. Porting that back to N3, with all the costs associated with that, makes no sense. Especially not when the final result would've been functionally an identical CPU thats still uncompetitive and low margin.

 

[igor_kavinski]

Shrinking to 18A defeats the entire purpose.

The point is to refine and improve 18A until it's ready for HVM (in other words, able to replace Intel 7, 4 and 3). Using a tried and tested older design helps them get there faster. Tick/tock cadence worked for them before because they tried not to chew too much by putting a new untested design on a brand new process. And now they are doing exactly that and the yields are in the gutter.

 

[DrMrLordX]

i definitely don't believe the clown for that part but i can believe Intel Forcing some developers to use More Modern Instruction or compiling with APX/AVX10.2

Intel doesn't have enough leverage to bully people into doing something like that. The only reason why future developers will consider supporting AVX10 seriously is that both AMD and Intel are adopting it (apparently) as a part of their x86 working group.

Using a tried and tested older design helps them get there faster.

Why? They already have Panther Lake as a pipecleaner product. They also have limited EUV capacity which has hampered Intel 4 and 3 volume and which will affect 18A volume in the future.

 

[igor_kavinski]

Why? They already have Panther Lake as a pipecleaner product.

When a brand new architecture based test chip comes back, how do they know that the bugs it is experiencing are from the architecture design flaws or the process? Using an older design that they know hasn't got any design flaws helps them weed out the process issues much quicker.

As an analogy, does a person who changes one overclocking parameter at a time, extensively tests that and only moves to changing the next parameter find more success than someone who messes with multiple parameters in a single go? Obviously yes.