Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[511]

What size did you measure Darkmont at?

Same as Skymont from the dies it's nearly the same. For Zen6C to be even equal to be skymont in area it has to be a massive shrink from N3E to N2 I don't see that happening. I doubt it's smaller than 5C at best it will be equal.

 

[511]

Or maybe never.

This is not true tbh it's coming. I am surprised MLID never leaked the name rouge river forest.

Also hyper scaler already get everything before anyone it's at hyperscalers in QS Samples.

 

[adroc_thurston]

This is not true tbh it's coming

Over half a year like dead.

 

[511]

It's not it never was that was a ploy 😛 and people took the bait.

 

[adroc_thurston]

It's not it never was that was a ploy 😛

It's literally dead.

 

[511]

You can believe that. I will believe what I want.

 

[adroc_thurston]

You can believe that.

I don't believe anything.
Oak Stream atom xeons are dodo.

 

[DavidC1]

18A's density isn't exactly like N3B/N3E. So there should be some changes.

As for Darkmont's contribution to power/area over Skymont it should be negligible. Really, I mean it's a teeny tiny change. This is like Penryn, or Westmere, or Broadwell. The E core has been Tick/Tocking for over ten years when the P core team gave it up years and years ago.

Multi-core gain wise, if they want a true server oriented CPU, they have to move onto a triple level caching scheme with L2 cache being discrete. The cluster setup is great for density but it hinders scaling. This is why Nehalem moved onto discrete L2 and shared L3.

 

[adroc_thurston]

they have to move onto a triple level caching scheme with L2 cache being discrete

Shared L2 is a-OK but they need to move from quads to duplexes.

 

[gdansk]

Same as Skymont from the dies it's nearly the same. For Zen6C to be even equal to be skymont in area it has to be a massive shrink from N3E to N2 I don't see that happening. I doubt it's smaller than 5C at best it will be equal.

There are 24 cores in 55mm². Did you look at the die shots? One might want to. Grab your pixel ruler and guesstimate.

 

[OneEng2]

Sounds like no objections so that's good. As long as we apply the same standard to both companies we do arrive at "months apart".

That is how I have it figured. As I stated, the majority (vast majority) of CWF life, it will be in competition with Venice Dense.

There are 24 cores in 55mm². Did you look at the die shots? One might want to. Grab your pixel ruler and guesstimate.

So ~ 2mm^2 Darkmont to ~3mm^2 Zen 6c (assuming that AMD adds transistors vs lowering die size going to N2)

Now, assuming that a DC customer cared about the PPA (which they largely do not. DC is notoriously unconcerned with price relative to other markets), this would still make the PPA about equal given Darkmonts lack of SMT.

Since area effeciency isn't really the metric DC customers are looking at, you still end up with a 256 core / 512 thread Zen 6c against a 288 core Darkmont. I'm figuring it would take a 384 core Darkmont to overtake Venice Dense.

 

[Joe NYC]

According to MILD, AMD is supposedly working on one

Bigger or smaller core?

 

[DavidC1]

There are 24 cores in 55mm². Did you look at the die shots? One might want to. Grab your pixel ruler and guesstimate.

We won't get completely accurate ones until we get a proper shot. Skymont based on Lunarlake block diagram was 1.3mm2. The actual die shot showed it was 1.1mm2. The biggest problem with Clearwater is the delay. Rest are really irrelevant from that point of view.

Since area effeciency isn't really the metric DC customers are looking at, you still end up with a 256 core / 512 thread Zen 6c against a 288 core Darkmont. I'm figuring it would take a 384 core Darkmont to overtake Venice Dense.

Timing is so crucial and they missed it with the 6 month delay. It would have been fantastic if it released this year. Regardless, this should be more competitive than predecessors. Sierra Forest played on the low end and had to compare with 64 core parts. Clearwater will be closer to Zen 6 Dense than Sierra Forest was to Zen 4 dense though.

 

[Joe NYC]

nonsense.
N2 almost certainly have limited wafers in 2026, so we see it as "Apple only".
Venice is 2027 product.

Again, TSMC and AMD had a big announcement of Venice being leading N2 product. Leading N2 product will definitely not be 2027 product.

You can zoom in on the text above the wafer

https://twitter.com/x/status/1911905838878388695

On similarly way, even if Diamond has ZERO bug, it is 2027 product.

DMR was originally planned for H2 2026. Then the CEO LBT said that it may be +/- 6 months so it may slip into 2027. My estimate would be 6 month lead of Venice ahead of DMR. But CWF may have up to 6 month lead vs. Zen 6.

 

[DavidC1]

That is how I have it figured. As I stated, the majority (vast majority) of CWF life, it will be in competition with Venice Dense.

So ~ 2mm^2 Darkmont to ~3mm^2 Zen 6c (assuming that AMD adds transistors vs lowering die size going to N2)

I'm getting 1.2-1.4mm2 based on that rough shot without the L2 cache.

That is how I have it figured. As I stated, the majority (vast majority) of CWF life, it will be in competition with Venice Dense.

This depends on Rogue River Forest. Original timeline was H2 2024 for Sierra Forest and H2 2025 for Clearwater Forest, so logically it would be H2 2026 for RRF. If it's H1 2027 since CWF is H1 2026, then it's split into 50/50 not majority.

 

[DavidC1]

Clearwater Forest clocks slightly higher

59TFlops for 576 cores.

With 64-bit compute, each core can compute 8x Flops per GHz. Let's assume 3GHz.
4x128-bit units x 128/64-bit x 3GHz x 576 cores = 13.8TF

So for the math to make sense, they are using FP16 for "AI". At 3GHz that equals to 55.3TFlops. To reach 59TFlops, it needs to be 3.2GHz, which is 200MHz higher than the peak frequency of Xeon 6780E Sierra Forest. There's potential to reach 3300 in 2P SpecIntRate, which is 2.3x SRF.

 

[gdansk]

I'm getting 1.2-1.4mm2 based on that rough shot without the L2 cache.

What image are using again? I had 2.2mm with 1/4th the L2 block. Maybe I messed up

 

[DavidC1]

What image are using again? I had 2.2mm with 1/4th the L2 block. Maybe I messed up

The weird image that we had few pages ago. Remember, that's for all 288 cores, not a single 24 core compute block.

It's roughly 164 by 225 pixels for the 55mm2 compute die. For this example, I'm including the purple borders, but not fully. The borders in between I'm only going about half way. It's 75 x 66 for the quad core cluster, which then becomes 1.84mm2. The cores are 29x30, which becomes ~1.3mm2. You have to refer to clear Skymont shots to see how to isolate. Anyway, it can't be 2.2mm, because it's smaller than that with L2 blocks included.

 

[gdansk]

Anyway, it can't be 2.2mm, because it's smaller than that with L2 blocks included.

So we're using the same tiny image. But how do you figure this? 55mm2 with 24 cores per SemiAnalysis. My measurement remains possible. But probably need to find a different image to have any real accuracy.

 

[DavidC1]

So we're using the same tiny image. But how do you figure this? 55mm2 with 24 cores per SemiAnalysis. My measurement remains possible. But probably need to find a different image to have any real accuracy.

Of course there are differences. We're trying to find out core sizes are we not?

If you take out the boundary altogether rather than including them 1/2, you get 48mm2. There are also gaps between the top 4 cluster and the bottom 2 cluster that doesn't exist in other places. You need extra to account for communication logic. That accounts for another 3.5mm2. Now we're down to 44mm2. That's 1.85mm2. When do we ever see SoC level die sizes that are exactly Core size x # of cores?

I gave an example of the Lunarlake block diagram shot that we were using it to calculate sizes and we got 1.3mm2 out of it. When we got the ACTUAL shot we got 1.1mm2.

 

[gdansk]

Of course there are differences. We're trying to find out core sizes are we not?

Nope, and maybe the fundamental difference here. I'm trying to find number of cores in a given chip size exclusive of LLC since that's what I measured for Z5C. In this metric I arrived at approximately 2.9/2.2. In that respect, internal non-scribal gaps (almost assuredly only a "gap" from low resolution imagery) would be irrelevant. From the 29x30 pixel image I have, I'm amazed anyone tried to measure it any other way.

 

[DrMrLordX]

This depends on Rogue River Forest. Original timeline was H2 2024 for Sierra Forest and H2 2025 for Clearwater Forest, so logically it would be H2 2026 for RRF. If it's H1 2027 since CWF is H1 2026, then it's split into 50/50 not majority.

Why would Intel be able to launch Rogue River Forest only one year after Clearwater Forest, given the lag between Sierra Forest and Clearwater Forest (and the ugly delays for Diamond Rapids as well)? That puts an awful lot of confidence in enterprise design teams that have been late on everything since Sapphire Rapids, in some cases grotesquely so.

 

[511]

Only time can tell that the only launch on schedule was GNR/SRF in last 10 years in DC.

 

[coercitiv]

Why would Intel be able to launch Rogue River Forest only one year after Clearwater Forest, given the lag between Sierra Forest and Clearwater Forest (and the ugly delays for Diamond Rapids as well)? That puts an awful lot of confidence in enterprise design teams that have been late on everything since Sapphire Rapids, in some cases grotesquely so.

If their aim with RRF is to replace compute tiles, then it should be doable. If the plan is to rebuild the lego stack... then obviously not that doable anymore.

 

[511]

If their aim with RRF is to replace compute tiles, then it should be doable. If the plan is to rebuild the lego stack... then obviously not that doable anymore.

They are only replacing the Compute tiles from Darkmont to Arctic Wolf also the IO tile will be on Intel 4/3 for DMR/RRF.

Clearwater -> IO Die I7(Reused with GNR/SRF) ,Base Die 3T,Compute 18A.
DMR -> IO Die I3/4, Base 3T, Compute(Reuse from Clearwater ?) -18AP
RRF -> IO Die I3/4, Base 3T(Reuse From Clearwater?), Compute - 18AP