Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Khato]

They want flexibility as well in terms of their schedule 18AP is later launch than N2 for Volume. Initial volume will go to DMR

I was wondering how long it'd take before someone remembered that Intel still has about 3/4 of server CPU sales. And 100% of Xeon CPUs are Intel silicon. I'd argue that Intel using their own process for the products which are going into the most competitive and lucrative market is a pretty good indicator of relative performance. Compared to the consumer market where maybe 10% of sales are influenced by actual performance metrics more than marketing?

 

[Kepler_L2]

I'd argue that Intel using their own process for the products which are going into the most competitive and lucrative market

AMD has same revenue and more profit than Intel in servers despite lower unit sales. Intel is selling things at cost to keep market share.

 

[jpiniero]

AMD has same revenue and more profit than Intel in servers despite lower unit sales. Intel is selling things at cost to keep market share.

There was a chart that a large potion of the sales was Cascade Lake even. That was Q4 2024.

 

[Geddagod]

I think N2P will be for Zen 6 for next year for sure, I just think N2X for a Zen 6+ Vs RZL in 2027 is plausible.

For AMD to actually take advantage of N2X, they would likely have to change the physical design of the core itself, and I also wonder how much of AMD's N2P node would already use features of the N2X node.
Conspiracy theory- the reason why Techinsights is claiming that Zen 5 is on N4X, multiple times (so not a typo), while AMD themselves only claim N4P, is because the custom node AMD uses actually already has many back-end features of N4X.

 

[Geddagod]

I was wondering how long it'd take before someone remembered that Intel still has about 3/4 of server CPU sales. And 100% of Xeon CPUs are Intel silicon. I'd argue that Intel using their own process for the products which are going into the most competitive and lucrative market is a pretty good indicator of relative performance. Compared to the consumer market where maybe 10% of sales are influenced by actual performance metrics more than marketing?

Client as a whole has been more lucrative than server, has been the case for a while, in terms of operating income and revenue.
Can this logic also be applied to GNR using Intel 3 vs ARL using TSMC N3? Have we been mistaken and Intel 3 was better than TSMC 3nm all along?

 

[igor_kavinski]

Can this logic also be applied to GNR using Intel 3 vs ARL using TSMC N3? Have we been mistaken and Intel 3 was better than TSMC 3nm all along?

AMD EPYC 9655 Benchmarks Show The Terrific Generational Gains With 5th Gen EPYC Review - Phoronix

www.phoronix.com

The single 96-core EPYC 9655 Turin processor was also often running similar or only slightly behind the 128-core Xeon 6980P Granite Rapids processors.

If a 128-core Xeon CPU on Intel 3 can't create comfortable distance between itself and an Epyc with a 32 core deficit, there is no way Intel 3 is superior. Had it been, the Xeon would've had higher all core clocks and no way could an Epyc give it a run for its money.

 

[511]

If a 128-core Xeon CPU on Intel 3 can't create comfortable distance between itself and an Epyc with a 32 core deficit, there is no way Intel 3 is superior. Had it been, the Xeon would've had higher all core clocks and no way could an Epyc give it a run for its money.

Not same design it's Golden Cove++ vs Zen 5. You need same design with proper DTCO with the cores

 

[igor_kavinski]

Not same design it's Golden Cove++ vs Zen 5. You need same design with proper DTCO with the cores

OMG, stop. Sell your Intel shares. It's over!

 

[Geddagod]

Not same design it's Golden Cove++ vs Zen 5. You need same design with proper DTCO with the cores

Zen 5 has no appreciable perf/watt uplift over Zen 4 in specint2017 at the power level these cores run at, and Turin Standard and GNR perform pretty much the same under a 500 watt TDP there too.
Intel 3 and N4P then are pretty comparable from that product perspective at least, though Intel should have some advantages using better packaging and fewer, larger chiplets to save on power.

 

[511]

Zen 5 has no appreciable perf/watt uplift over Zen 4 in specint2017 at the power level these cores run at, and Turin Standard and GNR perform pretty much the same under a 500 watt TDP there too.
Intel 3 and N4P then are pretty comparable from that product perspective at least, though Intel should have some advantages using better packaging and fewer, larger chiplets to save on power.

But can you proof that Redwood Cove is better than Zen 5 as a uArch which is clear as Zen 5 is superior than RWC.

 

[511]

OMG, stop. Sell your Intel shares. It's over!

🤣🤣

 

[Geddagod]

But can you proof that Redwood Cove is better than Zen 5 as a uArch which is clear as Zen 5 is superior than RWC.

Well that's why he also have the cushion of GNR having better memory support, better packaging, and fewer, larger tiles.
GNR has quite a bit of advantages that can offset any sort of core architectural disadvantage that would present itself vs Zen 5, at extremely low power levels (which Zen 5 has esentially no improvement over even Zen 4).
But the perf/watt argument is honestly the weakest point against Intel 3 not being a N3 contender, since tbf even N3 doesn't seem like a massive uplift over N5 there. What makes it look really bad is the area considerations. RWC is so much larger than Zen 4 that simply architectural/physical design can not possibly explain the margin.
And yes, it may use HP cells sure, but it is very possible to make an area efficient core while using larger libs, just look at the X925. It may also be the case that Intel had to use HP cells on Intel 3 to get the same perf/watt (at the medium-high end of the curve) and Fmax as AMD could do on HD with N4.

 

[oak8292]

Every Intel node in the last 10 years has faced delays, yield issues and had subpar PPA, you can't blame it all on a single decision.

There are delays and there are failures. I would put 10 nm in the failure category, it wasn’t just a delay in improving yields. There was enough time for full node development. Intel 4 nm went with enhanced Cu over Cobalt.

Intel 4 Process Drops Cobalt Interconnect, Goes with Tried and Tested Copper with Cobalt Liner/Cap - Semiconductor Digest

At the VLSI Symposia in June, Intel presented a paper “Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High Density and High-Performance Computing.” Blogger Dick James reports on details of the interconnect strategy.

www.semiconductor-digest.com