Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[reb0rn]

Do we even know if they will use emib or foveros maybe?

 

[511]

Foveros is pretty much guaranteed in NVL

 

[DrMrLordX]

because @dangerman1337 pointed issue with bLLC defect rate, its on same or very similar node, if AMD have no issue I see no intel problem here at all

That's false equivalence. There is no evidence of inevitable high defect rates for future cache dice.

 

[Fjodor2001]

if you cut that 4+8 in half ut becomes 4+0/8+0.

I suppose you mean it becomes 4+0/0+8?

But is it really possible to cut it like that and still get usable dies. I added some red lines in the picture. Do you mean it should be cut along those red lines, or some other way?



The 4 P cores would be on two separate dies after the cutting then.

Wouldn't cutting it in the middle to get two 2+4 dies be a more logical option instead?

 

[511]

I suppose you mean it becomes 4+0/0+8?

But is it really possible to cut it like that and still get usable dies. I added some red lines in the picture. Do you mean it should be cut along those red lines, or some other way?

View attachment 128536

The 4 P cores would be on two separate dies after the cutting then.

Wouldn't cutting it in the middle to get two 2+4 dies be a more logical option instead?

So the layout is a bit changed 2P Cores Shares a L2 Slice and also this is how i expect NVL Die Layout

 

[DKR]

IDK about SKU but the plan to make 4+8 using 18AP is canned it is using TSMC N2 now

Are you 100% confident about this? Because they already have a 4P+8E die on 18A for PTL-H? so it shouldn't be a big deal do that in 18A-P to do the same considering its just a related + node. At least what is what I thought. Also NVL is already taped out by the time Foundry direct connect 2025 event & shortly afterwards semiaccurate reported NVL SKUs on N2 taped out, I highly doubt Lip Bu Tan could have changed something on NVL by then.

Just from engineering POV to reduce engineering effort, to leverage tile arch & benefit from it, it makes sense to do one 8P+16E die on N2P & one 4P+8E die on 18A/18A-P. Then they can mix and match to create SKUs & down bin the 4+8 die to 4+4 & 4+0.
Note if 4+8 die is on 18A/18A-P, the entire mobile line up on NVL- H will be IFS (like PTL-H but on 18A-P), only the NVL-HX (8+16) will be on TSMC. I think this is very important for Intel to regain their margins. So it just baffles me that 4+8 would be on TSMC & that decision being made Lip Bu doesn't sound right with me. He is looking to be bean counter when it comes margins based on recent news about new product being approved only if margin >50%. Intel can't afford to keep outsourcing their products and maintain upkeep of their foundries which are fixed cost business.

This aligns with past commentaries from Pat & Michelle also that NVL is predominantly IFS based (Pat quoted >80% iirc) and only one top end SKU is on TSMC node. Also why MLID is keeping the 4+8 SKU as "high confidence" color instead of "very high confident" color. He is intentionally downplaying 18A-P imho.

I think Intel is only sourcing the 8P+16E bLLC die from TSMC. With that they can make a 2(8P+16E bLLC)+4LPE SKU for a Core Ultra 9, (8P+16E bLLC & 4P+8E[18A-P])+4LPE SKU for Core Ultra 7 & (8P+16E bLLC)+ 4LE for Core Ultra 5 that covers all the gaming crowd requirements of a bLLC SKU to compete with x3D. All these will be K SKUs. All the rest of the main stream K & non K SKUs will be based on 18A-P tiles like 2(4+8)+4LPE, 4+8+4LPE, 4+0+4LPE. This way they limit the outsourcing to TSMC to the minimum. This is just speculation on my part but who knows what is really going on at Intel now!

 

[DavidC1]

because @dangerman1337 pointed issue with bLLC defect rate, its on same or very similar node, if AMD have no issue I see no intel problem here at all

Caches are highly repetitive. It's the least defect rate prone part.

 

[511]

Are you 100% confident about this? Because they already have a 4P+8E die on 18A for PTL-H? so it shouldn't be a big deal do that in 18A-P to do the same considering its just a related + node. At least what is what I thought. Also NVL is already taped out by the time Foundry direct connect 2025 event & shortly afterwards semiaccurate reported NVL SKUs on N2 taped out, I highly doubt Lip Bu Tan could have changed something on NVL by then.

Yes 100%

 

[511]

Why are people making out about ~30mm2 extra die as bad defect rate its still < 150mm2 not a reticle size die also as DavidC1 said Cache aka SRAM can be worked around for bad yield using redundancy

 

[511]

https://twitter.com/x/status/1954809963307557267

another case of MLID Overhyping

 

[fastandfurious6]

IDK about SKU but the plan to make 4+8 using 18AP is canned it is using TSMC N2 now

this is the probable future for intel/usf, keep top-end chips on TSMC latest nodes and keep less performing on their overpromising underdelivering intel nodes