Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[MoistOintment]

5.1Ghz fMax makes sense. It explains PTL-S cancelation.

And if 18AP can get fMax up to the high 5Ghz range, a lot of rumors are pointing at N2X being in the low 6Ghz range, again explaining why top NVL-S die will use N2, with mobile and lower desktop due on 18AP.

 

[RTX]

Whoever told you this is freaking lying it's slightly smaller than LNC on N3B N3E HP 3-2 is less dense than 18A HP
View attachment 128437


RWC doesn't uses HD Libs classic Intel.

https://forums.anandtech.com/attachments/n3-fins-dielectric-png.128308/

Looks like N3B has ~5% denser sram while N3E has ~2% denser logic
173nm vs 169nm

 

[Joe NYC]

It includes Memory/Display Controller Media engine P/E/LP-E Cores and die waste unit

So, if Panther Lake goes back to having CPU cores share die with memory controllers, with Nova Lake, Intel is continuing Arrow Lake approach of having memory controllers on a separate die:

 

[511]

So, if Panther Lake goes back to having CPU cores share die with memory controllers, with Nova Lake, Intel is continuing Arrow Lake approach of having memory controllers on a separate die:

View attachment 128490

Yes

 

[511]

He is still wrong on the 4+8+4 SKU which is IFS also Raichu already leaked the halo die btw lol

 

[Thunder 57]

So, if Panther Lake goes back to having CPU cores share die with memory controllers, with Nova Lake, Intel is continuing Arrow Lake approach of having memory controllers on a separate die:

View attachment 128490

So the 18A looks to be low end only as has been rumored. That "APO+ rumor" though is so beyond bunk that it's laughable.

 

[511]

So the 18A looks to be low end only as has been rumored. That "APO+ rumor" though is so beyond bunk that it's laughable.

Uh no his node was leak was not correct?

 

[Thunder 57]

Uh no his node was leak was not correct?

So what parts will use N2 and which ones will use 18A?

 

[511]

So what parts will use N2 and which ones will use 18A?

8+16/8+16 bLLC - N2/N2P
4+8 -> N2P
4+0 -> 18AP
HUB -> 18A
iGPU Tile -> Xe3 reused from Panther Lake for desktop
edited some stuff

 

[511]

Maybe I can pin this I don't know I am tired of repeating leaked stuff

 

[Joe NYC]

8+16/8+16 bLLC - N2/N2P
4+8 -> N2P
4+0 -> 18AP
HUB -> 18A
iGPU Tile -> Xe3 reused from Panther Lake for desktop
edited some stuff

That's what MLID has as well. Except he has 4+0 as 18A, not 18AP

The the disaster, IMO, is that 4+8 and also 8+16 small L3 are all on TSMC. Those 2 dies are the bulk of the volume.

Also, taping out 4 separate CPU dies on 2 different process technologies just to serve the desktop segment does not seem very efficient, especially after all the job cuts.

 

[511]

That's what MLID has as well. Except he has 4+0 as 18A, not 18AP

The the disaster, IMO, is that 4+8 and also 8+16 small L3 are all on TSMC. Those 2 dies are the bulk of the volume.

Also, taping out 4 separate CPU dies on 2 different process technologies just to serve the desktop segment does not seem very efficient, especially after all the job cuts.

Ehh the die is very well designed to make it 8+16/4+8/4+0 for the entire purpose here is the 8+16 die if you cut it in half it becomes 4+8 and if you cut that 4+8 in half ut becomes 4+0/8+0.

This is just for reference the layout has changed a bit in NVL but it's similar.

 

[Thunder 57]

That's what MLID has as well. Except he has 4+0 as 18A, not 18AP

The the disaster, IMO, is that 4+8 and also 8+16 small L3 are all on TSMC. Those 2 dies are the bulk of the volume.

Also, taping out 4 separate CPU dies on 2 different process technologies just to serve the desktop segment does not seem very efficient, especially after all the job cuts.

I expect to see 18A on the lower end desktop chips and perhaps a sizable amount of laptop chips. Nothing to back that up, just what I'm feeling.

 

[DZero]

That's what MLID has as well. Except he has 4+0 as 18A, not 18AP

The the disaster, IMO, is that 4+8 and also 8+16 small L3 are all on TSMC. Those 2 dies are the bulk of the volume.

Also, taping out 4 separate CPU dies on 2 different process technologies just to serve the desktop segment does not seem very efficient, especially after all the job cuts.

And even worse, what if the 4+0 ends to be the better option considering the price? The bulk ends to be a BIG marketing dissaster at the end.

 

[Geddagod]

8+16/8+16 bLLC - N2/N2P
4+8 -> N2P
4+0 -> 18AP
HUB -> 18A
iGPU Tile -> Xe3 reused from Panther Lake for desktop
edited some stuff

Idk, I expect it to look like this (based on leaks I have seen, I could have missed some):
8+16 bLLC N2 (NVL)
8+16 N2 (NVL)
4+8 18A-P

I expect to see 18A on the lower end desktop chips and perhaps a sizable amount of laptop chips. Nothing to back that up, just what I'm feeling.

I think it depends on how AMD segments Zen 6 mobile.
If only the AI 9 sku has the 12 core CCD, and the rest of the skus use just the IOD, a 4+8+4 Intel setup can be competitive with a 4+4+2 AMD setup. But also depends on how hard the AI 9 skus also get pushed, I think they top tier skus get pushed more in laptops than they do in desktop.

 

[511]

Idk, I expect it to look like this (based on leaks I have seen, I could have missed some):
8+16 bLLC N2 (NVL)
8+16 N2 (NVL)
4+8 18A-P

Same but 4+8 got moved to N2P among cuts and plan changes after Tan he changed few things.
Even I got to know today lmfao anyway

 

[511]

https://twitter.com/x/status/1954165775096336734

 

[Geddagod]

Same but 4+8 got moved to N2P among cuts and plan changes after Tan he changed few things.
Even I got to know today lmfao anyway

Why though?
No way Intel has that little confidence in 18A-P.
Even if they think they couldn't get 18A-P out in time, making it on 18A likely won't necessitate any ports/changes since they should be IP compatible with each other, like Intel 3 and Intel 4 are.
There shouldn't be any Fmax concerns either since 18A already appears serviceable at north of 5GHz.
18A capacity should be ramping fast already since it should be out in products even earlier than TSMC N2. And they already invested a bunch of money into the buildout of 18A already, why delay or slow it down?

The only reason I can think of is that Intel wants to take the lead in the mid range laptop segment too. They might have a perf/watt or battery life advantage by using N2 there rather than AMD's N3. Perhaps I'm missing something.

 

[511]

Why though?
No way Intel has that little confidence in 18A-P.
Even if they think they couldn't get 18A-P out in time, making it on 18A likely won't necessitate any ports/changes since they should be IP compatible with each other, like Intel 3 and Intel 4 are.
There shouldn't be any Fmax concerns either since 18A already appears serviceable at north of 5GHz.
18A capacity should be ramping fast already since it should be out in products even earlier than TSMC N2. And they already invested a bunch of money into the buildout of 18A already, why delay or slow it down?

Ask Intel also Intel's 18A ramp capacity has been toned down from Initial estimates that's the only thing I know and the funny thing all the GPU Tiles are Intel lmao.

Even politicians are against Intel 🤣🤣. Imagine spending Billions in your country and getting problems in exchange.

 

[Tigerick]

https://twitter.com/x/status/1954165775096336734

Geez, PTL-H only comes with 4+4+4 (18A) core count

And NVL mobile will come with 4+8+4 fabbed by N2 (either cut from 8+16 or new die). Is my understanding correct?

 

[511]

Geez, PTL-H only comes with 4+4+4 (18A) core count

these are another SKU along with this

https://twitter.com/x/status/1887856347498320330

And NVL mobile will come with 4+8+4 fabbed by N2 (either cut from 8+16 or new die). Is my understanding correct?

4+8 is fabbed by TSMC yes and it's basically 8+16 die cut in half

 

[Joe NYC]

And even worse, what if the 4+0 ends to be the better option considering the price? The bulk ends to be a BIG marketing dissaster at the end.

4+0 could be a better option than 4+8 if the clock speeds were nearly the same, but my guess is that the reason 4+8 is on TSMC N2 is because 18A does not reach the desired clock speeds, so 4+0 might be sold with lower clock speed specs

 

[511]

4+0 could be a better option than 4+8 if the clock speeds were nearly the same, but my guess is that the reason 4+8 is on TSMC N2 is because 18A does not reach the desired clock speeds, so 4+0 might be sold with lower clock speed specs

it's 18AP a '+' and Intel's plus traditionally fixed frequency issues Intel has another problem that is TRUMP is seeing Intel as a way to save his name in history so that he is treated as a hero Intel has become a political playground as well among other stuff

 

[Tigerick]

these are another SKU along with this

https://twitter.com/x/status/1887856347498320330

4+8 is fabbed by TSMC yes and it's basically 8+16 die cut in half

Hoho, I really hope you are not so naive about Intel roadmap. That past configuration might not valid: it might be combination of PTL and NVL:

	Node	CPU	GPU	NPU
PTL-H	Intel 18-A	4 + 4 + 4	10 Xe (N3E)	50
NVL-H	N2	4 + 8 + 4	12 Xe (N3E)	?
NVL-S Core Ultra 3	N2	4 + 8 + 4	2 Xe (Intel 3)

Why do you think Intel rather use cut die of N2 to create low cost Ultra3 if 18-A is OK. As I said, 18-A sucks...that's only logical explanation.

Remember I told you PTL will experience many hiccups: cutting 4 e cores are actually worse than MTL's CPU. At least MTL shipped with full die of 6+8. To me, PTL pretty much is DOA, so much for process leadership...

 

[Magio]

https://twitter.com/x/status/1954165775096336734

8+16+4 mobile part? That's going to be interesting.