Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[511]

Not as bad as I thought, but also lmao@Semiwiki and everyone else who parroted "18A is faster than N2P"

Well read the article it says 5.2 GHz lol

 

[poke01]

how are they at par freq wise with TSMCs worst node....

 

[511]

how are they at par freq wise with TSMCs worst node....

It will take them a '+' to fix this thing aka 18AP and the reason for outsourcing to TSMC makes total sense now

 

[Geddagod]

It will take them a '+' to fix this thing aka 18AP and the reason for outsourcing to TSMC makes total sense now

NVL will likely use 18A-P, so if Fmax gets fixed, how does outsourcing to TSMC still make sense?

Not as bad as I thought,

Yes we know lol

 

[Geddagod]

PTL is 5.1GHz apparently

Usable Fmax. Maybe better than the 10nm+ scenario, worse than Intel 4 scenario?

 

[511]

Usable Fmax. Maybe better than the 10nm+ scenario, worse than Intel 4 scenario?

It matches MTL (Intel 4)

NVL will likely use 18A-P, so if Fmax gets fixed, how does outsourcing to TSMC still make sense?

18AP aka NVL Fmax is still ain't decided just like PTLs so taking a safe bet or so to say backup plan

 

[Geddagod]

It matches MTL (Intel 4)

I was talking more about the relative Fmax of the new node vs the Fmax of the older, more mature node.
So for 10nm it would have been Fmax of ICL vs Fmax of 14nm products, For Intel 4 it would be Fmax of MTL vs RPL, and for this it would be Fmax of PTL on 18A vs ARL.

18AP aka NVL Fmax is still ain't decided just like PTLs so taking a safe bet or so to say backup plan

Traditionally the "+" nodes have been very good at fixing Fmax problems.
And lets not forget, 18A-P isn't just the first plus, since 18A is just a large "+" over 20A too.
At some point it has to start becoming less about the "backup plan" and just knowing when your node is worse lol. Maybe it makes sense for ARL, maybe there's even a chance for PTL, but by NVL this is the 3rd generation of the 20A base node...

 

[jpiniero]

I have trouble believing IFS can continue to exist on legacy nodes alone. Sooner or later their own products wouldn't require those nodes, and if they struggle to compete in the foundry space at the cutting edge I don't fancy their chances on mature nodes.

If they were serious about being a third party foundry, that would be a big part of the plan.

 

[511]

So for 10nm it would have been Fmax of ICL vs Fmax of 14nm products, For Intel 4 it would be Fmax of MTL vs RPL, and for this it would be Fmax of PTL on 18A vs ARL.

What would you call RPL vs ARL with -0.5 Ghz?

Traditionally the "+" nodes have been very good at fixing Fmax problems.
And lets not forget, 18A-P isn't just the first plus, since 18A is just a large "+" over 20A too.
At some point it has to start becoming less about the "backup plan" and just knowing when your node is worse lol. Maybe it makes sense for ARL, maybe there's even a chance for PTL, but by NVL this is the 3rd generation of the 20A base node.

The nodes have to enter into a decent volume they need to run a good chunk of wafers. I don't know how much dev effort was put into 20A before jumping to 18A cause Intel 4 was fully completed did they abandon the 20A half way or what Ice Lake(10nm+) shipped worse than 14nm++++ in terms of frequency TGL was solid improvement.

20A never had actual volume materialize so I don't know if you want to call 18A a (20A+) it shares the dev effort for sure but it never launched not a single broken product to call it a node .

If Node development is so easy and predictable why don't every company do it lol no one knows ahead of time how a particular node is going to turn out It's a good thinking on Intel Product's part regarding their planning.

TSMC did a similar thing N2P was supposed to have BSPDN but they cut the BSPDN for later a minor improvement on N2P (~2-3%) over N2 according to TSMC and A16 get the BSPDN.

 

[Geddagod]

What would you call RPL vs ARL with -0.5 Ghz?

More of a difference between Intel 18A and Intel 7 lol.

The nodes have to enter into a decent volume they need to run a good chunk of wafers. I don't know how much dev effort was put into 20A before jumping to 18A cause Intel 4 was fully completed did they abandon the 20A half way or what Ice Lake(10nm+) shipped worse than 14nm++++ in terms of frequency TGL was solid improvement.

They didn't ship any 10nm silicon either. CNL was a meme.
18A should be equivalent to 10nm+, and 18AP to 10nm SF.
Besides, I thought you said 20A was canned due to costs, and not due to development?

If Node development is so easy and predictable why don't every company do it lol no one knows ahead of time how a particular node is going to turn out It's a good thinking on Intel Product's part regarding their planning.

No, its them knowing 18AP is worse than N2 by a good bit.
Again, you can't call every time Intel goes external as them "risk mitigating" lol. 18A-P is just more mature 18A, there is no risk there.
It's good thinking for Intel products to use a better node.

 

[Geddagod]

TSMC did a similar thing N2P was supposed to have BSPDN but they cut the BSPDN for later a minor improvement on N2P (~2-3%) over N2 according to TSMC and A16 get the BSPDN.

What is this even a similar thing to lol

 

[vanplayer]

View attachment 128431
PTL is 5.1GHz apparently

https://www.zhihu.com/question/1936359085550318318/answer/1936380500546683598

These people are just guessing and nobody nail down the frequency, internal target down from 5.4-5.5 to 5.0-5.1

also someone mentioned the density is comparable to N4X which is similar to what I heard last year, to be precised and AFAIK, Panther P core cluster is less dense than Granite Ridge Zen5 core cluster. I can't provide a number here but it's relevant to MTr/mm2.

 

[511]

They didn't ship any 10nm silicon either. CNL was a meme.
18A should be equivalent to 10nm+, and 18AP to 10nm SF.
Besides, I thought you said 20A was canned due to costs, and not due to development?

Yes and running wafers costs money

also someone mentioned the density is comparable to N4X which is similar to what I heard last year, to be precised and AFAIK, Panther P core cluster is less dense than Granite Ridge Zen5 core cluster. I can't provide a number here but it's relevant to MTr/mm2.

Lmfao Intel 3 is more than par with N4X in density 18A has density in the same ballpark as N3B which is the densest N3 node in terms of CPU design using HP libs.

 

[msj10]

These people are just guessing and nobody nail down the frequency, internal target down from 5.4-5.5 to 5.0-5.1

also someone mentioned the density is comparable to N4X which is similar to what I heard last year, to be precised and AFAIK, Panther P core cluster is less dense than Granite Ridge Zen5 core cluster. I can't provide a number here but it's relevant to MTr/mm2.

you said NVL bLLC doesn't exist a few days ago which is complete BS.

 

[Geddagod]

Lmfao Intel 3 is more than par with N4X in density

More than on par? It's on par at best given how RWC looks like.

18A has density in the same ballpark as N3B

18A HD is as dense as N3E HP from cell area. I think it's safe to assume it's less dense. Real question is just how bad is it.

 

[Joe NYC]

These people are just guessing and nobody nail down the frequency, internal target down from 5.4-5.5 to 5.0-5.1

also someone mentioned the density is comparable to N4X which is similar to what I heard last year, to be precised and AFAIK, Panther P core cluster is less dense than Granite Ridge Zen5 core cluster. I can't provide a number here but it's relevant to MTr/mm2.

I was trying to figure out transistor density of either Arrow Lake or Lunar Lake compute die - with no luck. Any ideas / estimates?

 

[511]

18A HD is as dense as N3E HP from cell area. I think it's safe to assume it's less dense. Real question is just how bad is it.

Whoever told you this is freaking lying it's slightly smaller than LNC on N3B N3E HP 3-2 is less dense than 18A HP

More than on par? It's on par at best given how RWC looks like.

RWC doesn't uses HD Libs classic Intel.

 

[vanplayer]

Lmfao Intel 3 is more than par with N4X in density 18A has density in the same ballpark as N3B which is the densest N3 node in terms of CPU design using HP libs.

Sometimes I thought it's not the node's problem, but it's the design that being problem, Intel's whatever CPU and GPU being less dense than competition even when on the theoretical competitive node.

The example is Intel7 loses 40% density compare to on-paper number when it's on Alderlake, another example is Battlemage's PPA is terrible.

you said NVL bLLC doesn't exist a few days ago which is complete BS.

¯\_(ツ)_/¯

 

[511]

Sometimes I thought it's not the node's problem, but it's the design that being problem, Intel's whatever CPU and GPU being less dense than competition even when on the theoretical competitive node.

The example is Intel7 lose 40% density compare to on-paper number when it's on Alderlake, another example is Battlemage's PPA is terrible.

Yeah same thought many times though for the CPU Core the density was fine for the other stuff it ain't fine

 

[poke01]

I wouldn’t fully trust rumours regarding Panther lake, too many vultures circling Intel. Just gotta wait and see from Intel themselves

 

[511]

I wouldn’t fully trust rumours regarding Panther lake, too many vultures circling Intel. Just gotta wait and see from Intel themselves

who needs vulture when the president of your own country is after you

 

[Geddagod]

Whoever told you this is freaking lying it's slightly smaller than LNC on N3B N3E HP 3-2 is less dense than 18A HP

Wikichip

48 x 169 = cell area of 8112.
Intel 18A HD cell area is 50 x 160 = 8000.
Pretty much the same.

RWC doesn't uses HD Libs classic Intel.

Very little difference between HD and HP Intel 3 density. Not much cell height scaling. Similar to 18A in that sense.

I wouldn’t fully trust rumours regarding Panther lake, too many vultures circling Intel. Just gotta wait and see from Intel themselves

What they said wasn't even that bad lowkey

 

[Joe NYC]

Sometimes I thought it's not the node's problem, but it's the design that being problem, Intel's whatever CPU and GPU being less dense than competition even when on the theoretical competitive node.

The example is Intel7 loses 40% density compare to on-paper number when it's on Alderlake, another example is Battlemage's PPA is terrible.



¯\_(ツ)_/¯

I agree with this.

And then all the discussion about theoretical density are moot. If the only product on it Panther Lake and that design can't reach this density, not even close, than what's the point of discussing it?

BTW, does Panther Lake compute tile include memory controllers or only cores? The reason I am curious is if we can even theoretically get a good measure. Because inclusion of memory controllers would likely dilute the transistor density...

 

[511]

BTW, does Panther Lake compute tile include memory controllers or only cores? The reason I am curious is if we can even theoretically get a good measure. Because inclusion of memory controllers would likely dilute the transistor density...

It includes Memory/Display Controller Media engine P/E/LP-E Cores and die waste unit

 

[OneEng2]

His primary objective is stopping the bleeding of cash and actually helping Intel turn a profit. The mess created by Pat is just too insane:

trying to sell existing Raptor Lake inventory (even Alder Lake is still not sold out),

dealing with RPL RMAs,

Intel 7 still being a harsh reality to deal with because those fabs were not converted to Intel 3 or 4,

trying to woo back OEMs because Pat's decisions led them to look to AMD to fulfill their mobile products demand,

trying to trim Pat's fat engineering teams to make them more lean and agile

and so many other problems that are probably not even public and which contributed to Pat's sudden termination.

IMO, his worst mistake was ignoring the exponentially rising cost of lithography processes and machinery and attempting to compete with TSMC's volumes at a fraction of their volume.

People keep assuming that it is less expensive for Intel to make its own chips on 18A when Intel put over 20bn into the development of that process (as I have said before, this is as much as a Ford class Navy aircraft carrier).

This is simply unsustainable ..... even IF 18A would have achieved parity with N2.

NVL will likely use 18A-P, so if Fmax gets fixed, how does outsourcing to TSMC still make sense?

It is likely less expensive to make chips on 18A/18A-P only if sunk costs are ignored. My guess is that the performance and yield and volume are lacking. This not only leaves TSMC making sense, it likely leaves it as the only option unfortunately.

I was talking more about the relative Fmax of the new node vs the Fmax of the older, more mature node.
So for 10nm it would have been Fmax of ICL vs Fmax of 14nm products, For Intel 4 it would be Fmax of MTL vs RPL, and for this it would be Fmax of PTL on 18A vs ARL.

Traditionally the "+" nodes have been very good at fixing Fmax problems.
And lets not forget, 18A-P isn't just the first plus, since 18A is just a large "+" over 20A too.
At some point it has to start becoming less about the "backup plan" and just knowing when your node is worse lol. Maybe it makes sense for ARL, maybe there's even a chance for PTL, but by NVL this is the 3rd generation of the 20A base node...

I am not certain that it makes any sense from a financial standpoint. New process tech development has become exponentially more expensive and more difficult to get right.

Whoever told you this is freaking lying it's slightly smaller than LNC on N3B N3E HP 3-2 is less dense than 18A HP

It is my understanding that BSPDN allows routing efficiencies of ~30% that are not included in the raw density calculations.