Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[gdansk]

Seriously, you think 24 cores Zen 6 are going to run at the same clock (or higher!!!) as 16 Zen 5 cores at the same power?

It is more likely than you think. But even if they must follow Intel's lead on PL2 increase they end up with exactly the same power per core as they have now (16C @ 200W => 24C @ 300W).

 

[adroc_thurston]

you think 24 cores Zen 6 are going to run at the same clock (or higher!!!) as 16 Zen 5 cores at the same power?

yeah man it's called a double shrink.

 

[DavidC1]

I look at it this way:
Zen 6 24 core with HT (add 1/3 for HT, probably a generous estimate) = 32 core equivalent
NL, if it actually materializes, 16 P cores, 32 E cores (estimate 60% of P core, could be better) give approx 20 equivalent P cores = 36 core equivalents

In Arrowlake, it's already way better than 60%. It's ~10% per clock advantage with 23% clock, so about 0.75x.

In Novalake I expect that gap to close further, maybe to 0.85x.

But overall I expect two vendors to be not too far from each other, why? Because having that many cores needs lower clocks.

So if it's (16P + 32 X 0.85) * 0.8, we get ~34 which is ballpark similar to your Zen 6 estimate. I don't think HT gains will be that high either, but that'll be made up by Zen 6's uarch gains.

The fact that there's more threads on Novalake runs into more diminishing returns, because more applications will scale less from it. There's that too.

 

[DavidC1]

Lunarlake handheld review: https://www.techpowerup.com/review/claw-8-ai-a2vm/9.html

The MSI Lunarlake shows a consistent ~4W lower power from the Zotac AMD 8000 chips, at same set TDP level.

I think this is similar to Apple chips showing great power advantage especially at lower power levels. It's uncore/platform level power difference, which is why there's little variance between high and lower power levels.

This is why Lunarlake gets a disproportionate advantage in lower power levels, because that 4W is a bigger portion at 10W than it is at 30W. Advantage in battery goes from 80% to 116% with a 65% battery capacity difference.

No, only an Asus laptop and a DIY desktop with LNC/Skymont to test. Plus I don't own that game. So I can't test this specific scenario. Maybe I can try to set the TDP lower, perhaps that's cause here.

I don't get this. Are you saying you have LNC/SKT on both of the devices?

Yes lower power settings will make a difference.

According to that screenshot, SKT config is getting 41 fps at 24W system power while LNC config is getting 35 fps at 27W system power. I would say this is quite conclusive that SKT is actually quite power efficient, unlike the split opinions of GMT, the predecessor.

 

[adroc_thurston]

It's uncore/platform level power difference, which is why there's little variance between high and lower power levels.

you do know that LNL is N3 right

 

[Fjodor2001]

The fact that there's more threads on Novalake runs into more diminishing returns, because more applications will scale less from it. There's that too.

No, because on Zen6 there is 24C/48T, i.e. same thread count as on NVL-S 48C/48T. Excluding LP cores on both.

 

[gdansk]

According to that screenshot, SKT config is getting 41 fps at 24W system power while LNC config is getting 35 fps at 27W system power. I would say this is quite conclusive that SKT is actually quite power efficient, unlike the split opinions of GMT, the predecessor.

I am saying I am completely unable to replicate this in any game I have tried on my 226V LNL device. Admittedly I haven't tried at sub 28W PL yet.

 

[DavidC1]

No, because on Zen6 there is 24C/48T, i.e. same thread count as on NVL-S 48C/48T. Excluding LP cores on both.

Yup, corrected.

But the other parts apply such as needing to use essentially same process to power 2x the cores.

I am saying I am completely unable to replicate this in any game I have tried on my 226V LNL device. Admittedly I haven't tried at sub 28W PL yet.

And what do you have? Lunarlake lappy and Arrowlake desktop?

Cause you know core level power differences get muted when the non-SoC power is greater right? So Arrowlake will show less gains from core than in Lunarlake.

And yes lower power will make a difference.

you do know that LNL is N3 right

It makes no difference in platform power. Every CPU could power gate since at least Nehalem in 2010.

 

[adroc_thurston]

It makes no difference in platform power

yeah it does.

Every CPU could power gate since at least Nehalem in 2010.

It's a video game, it's not letting you power gate much (if any) of the SOC.

 

[DavidC1]

yeah it does.

It's a video game, it's not letting you power gate much (if any) of the SOC.

This folks is why ARM still has a massive battery life advantage...

 

[adroc_thurston]

This folks is why ARM still has a massive battery life advantage...

In video games?

 

[DavidC1]

yeah it does.

Yea, cause that made a difference for Arrowlake, yet it did make a difference for Lunarlake.

Under load it's smaller, but it still exists, because IO doesn't have a dynamic range as large as cores do, it's way less.

In video games?

I'm saying that kind of thinking is likely pervasive in the x86 world including engineers.

You cut Idle from 4W to 1W, it'll also cut load power by approximately the same amount. Hence under low power systems, it becomes a substantial advantage. If you are making a 10W and under CPU, cutting platform idle power is just as important as cutting CPU core power.

 

[poke01]

You cut Idle from 4W to 1W, it'll also cut load power by approximately the same amount. Hence under low power systems, it becomes a substantial advantage. If you are making a 10W and under CPU, cutting platform idle power is just as important as cutting CPU core power.

I'd be interested to see how Panther Lake handles the lower end of the curve, its supposed to be the same as Lunar Lake.

 

[igor_kavinski]

its supposed to be the same as Lunar Lake.

It's a new process and an Intel one at that. I think there might be some surprises in store for us.

 

[adroc_thurston]

cause that made a difference for Arrowlake

It did.

it'll also cut load power by approximately the same amount

No it does not.
That's not how fabrics work.

 

[gdansk]

I finally found a game where Skymont was a bit better than Lion Cove even at ~28W.

Lion Cove:

Spoiler

Skymont:

Spoiler

But it's better by giving the GPU more power. The CPU render and simulation results are better on LNC, but it starved the GPU occasionally.

 

[igor_kavinski]

Excellent work.



It annoys the hell out of me that Intel decided to cripple Lion Cove with no SMT because that could've been its saving grace.

In fact, even having SMT on Skymonts would've given "free" performance.

I think one possibility for fewer Skymont stutters in this instance is the shared cluster cache that allows the four Skymont threads to work more efficiently in parallel but obviously the data set needs to be small enough to fit in the cache.

 

[gdansk]

It annoys the hell out of me that Intel decided to cripple Lion Cove with no SMT because that could've been its saving grace.

I do not think SMT is helpful here. It's basically showing that the power split is better for gaming with Skymont instead of Lion Cove

But at lower settings LNC pulls away because GPU performance is less of a limiting factor.

Lion Cove, lowest:

Spoiler

Skymont, lowest:

Spoiler

 

[poke01]

I do not think SMT is helpful here. It's basically showing that the power split is better for gaming with Skymont instead of Lion Cove

But at lower settings LNC pulls away because GPU performance is less of a limiting factor.

Lion Cove, lowest:

Spoiler

View attachment 128278

Skymont, lowest:

Spoiler

View attachment 128277

This right here is why Unified core is years away. Yes Lion cove is bad but Skymont is not a suitable replacement for it. It’s just too weak to be a performance core.

It would also be good to know the power consumption of Skymont and Lion cove during this test.

 

[reb0rn]

For skymount to replace a Lion cove, it would need to be similar with zen6 core... more or less

 

[igor_kavinski]

It’s just too weak to be a performance core.

Probably in ST but suppose they created a Skymont-only CPU tile that had two clusters (each 4 monts) sharing a single L3. Assuming this megacluster took up the space of two Lion Cove cores, we could have 32 Skymonts in roughly the same space taken up by the 8+16 Arrow Lake compute tile. Add a bLLC as an L4 cache and it could be a pretty potent multicore monster.

 

[DavidC1]

No it does not.
That's not how fabrics work.

Fabrics work exactly that way. Anything that needs communication is difficult to throttle because every data has to be on it, even during low activity.

It's like cutting off a highway under low traffic periods.

I think one possibility for fewer Skymont stutters in this instance is the shared cluster cache that allows the four Skymont threads to work more efficiently in parallel but obviously the data set needs to be small enough to fit in the cache.

For multicore scaling separate L2 cache per core with shared L3 is better. Sharing causes contention which causes loss in bandwidth and increase in latency. Shared caches for L2 is a compromise between power, die area, and performance.

 

[Tarkin77]

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

"Yet only a small percentage of the Panther Lake chips printed via 18A have been good enough to make available to customers, said the two people, who were briefed on the company's test data since late last year. The sources spoke on condition of anonymity because Intel did not authorize them to disclose such information.This percentage figure, known as yield, means Intel may struggle to make its high-end laptop chip profitably in the near future."

 

[poke01]

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

"Yet only a small percentage of the Panther Lake chips printed via 18A have been good enough to make available to customers, said the two people, who were briefed on the company's test data since late last year. The sources spoke on condition of anonymity because Intel did not authorize them to disclose such information.This percentage figure, known as yield, means Intel may struggle to make its high-end laptop chip profitably in the near future."

why is it always reuters?

 

[Magio]

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

"Yet only a small percentage of the Panther Lake chips printed via 18A have been good enough to make available to customers, said the two people, who were briefed on the company's test data since late last year. The sources spoke on condition of anonymity because Intel did not authorize them to disclose such information.This percentage figure, known as yield, means Intel may struggle to make its high-end laptop chip profitably in the near future."

10% PTL yields by the summer sounds so catastrophically low I don't even know how they could launch PTL (even in limited volume) by early 2026 if it's an accurate figure.

why is it always reuters?

It's been clear since last summer that the contingent within Intel that wants to give up manufacturing has been strategically leaking info to Reuters to drive their narrative. It started out with with the "Broadcom doesn't like 18A" and "Intel missed out on PS6" stories, both of which were dubious in the framing of some of the information presented, that paved the way for Gelsinger's dismissal and has continued since.

Now, just because there seems to be a goal behind that constant stream of stories doesn't mean they're not accurate. But the good thing with this one is that if it's true, PTL cannot and will not launch near its planned window.