Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[dullard]

To be 1.15 to 1.2x above that would be 1.48x to 1.54x. Eclipsing even the great Zen 5 hype train, though unintentionally.

You are misreading his post. I'll edit it for clarity by adding the word "then":
"If they not screw it up and increase gaming perf by 15-20%. Then vs 9800X3D it would be a win."

The post doesn't make sense the way you read it (and as you point out that would be highly unlikely to occur). "Increase X by 15% vs Y" is just poorly written but in no way should it be read as "increase X until it is 15% more than Y".

 

[Joe NYC]

So the big Cache chiplet is 144MB the non cache one is 36 MB iirc.

Interesting. So Intel has to make a whole new die for this, new masks, verification etc?

It looks like another example of inefficiency at Intel...

 

[LightningZ71]

After reading the Phoronix review of the Epyc 4005, I have to wonder if Intel's dual CPU chiplets part is more targeted at being more competitive in the Entry level server/low end workstation market? The current offering is Raptor Lake with the e-cores disabled against AMD 16 core beasts. Maybe they will do a Nova lake 16 P-core part for that market now?

 

[jpiniero]

After reading the Phoronix review of the Epyc 4005, I have to wonder if Intel's dual CPU chiplets part is more targeted at being more competitive in the Entry level server/low end workstation market? The current offering is Raptor Lake with the e-cores disabled against AMD 16 core beasts. Maybe they will do a Nova lake 16 P-core part for that market now?

I think that was the point of Bartlett Lake.

 

[511]

Interesting. So Intel has to make a whole new die for this, new masks, verification etc?

It looks like another example of inefficiency at Intel...

I don't know for sure what's the deal with it in terms of design is it hybrid bonded or are they just extending the die somehow.

 

[Joe NYC]

I don't know for sure what's the deal with it in terms of design is it hybrid bonded or are they just extending the die somehow.

I think there was a statement from Intel exec that they will not have V-Cache equivalent imminently (in NVL), which would imply need for a new die.

 

[Doug S]

That'd be nearly a 1.4x increase in gaming performance relative to the 285K. What is it with speculators and 40%

If you're going to have wild dreams who is going to wildly dream about 9%

 

[Fjodor2001]

You undestand that by your own admission it is not additional cores that help, but placing them on the right CCD? So the additional cores do not convey additional benefit?

You're stuck in the present. It's a chicken and egg scenario. We need to look ahead into the future.

CPUs with more cores need SW that can use those additional cores. And SW that can make use of more cores need CPUs with more cores.

Your claim is that we're currently in a state where (some) SW can use 8C to 16C, but not much beyond that. Now rewind to the 4C area. Similarly some claimed that SW was not making use of more than 2-4C then, so we should not go beyond that. What would have happened if CPU manufacturers had followed that advice? We'd be stuck at 2-4C. And the SW you say nowadays make use of 8-16C would never have been developed.

Same situation now. Just that the limit is claimed (by some) to be 8-16C instead of 2-4C.

So we need either the chicken or egg to progress, so we get more than 8-16C on standard desktop CPUs. Then SW will follow to make use of those additional cores.

 

[Thunder 57]

You're stuck in the present. It's a chicken and egg scenario. We need to look ahead into the future.

CPUs with more cores need SW that can use those additional cores. And SW that can make use of more cores need CPUs with more cores.

Your claim is that we're currently in a state where (some) SW can use 8C to 16C, but not much beyond that. Now rewind to the 4C area. Similarly some claimed that SW was not making use of more than 2-4C then, so we should not go beyond that. What would have happened if CPU manufacturers had followed that advice? We'd be stuck at 2-4C. And the SW you say nowadays make use of 8-16C would never have been developed.

Same situation now. Just that the limit is claimed (by some) to be 8-16C instead of 2-4C.

So we need either the chicken or egg to progress, so we get more than 8-16C on standard desktop CPUs. Then SW will follow to make use of those additional cores.

Who? Show me who. You can't, because no one has ever made that claim. Stop making up crap to push a false narratitve.

 

[dullard]

You're stuck in the present. It's a chicken and egg scenario. We need to look ahead into the future.

CPUs with more cores need SW that can use those additional cores. And SW that can make use of more cores need CPUs with more cores.

Your claim is that we're currently in a state where (some) SW can use 8C to 16C, but not much beyond that. Now rewind to the 4C area. Similarly some claimed that SW was not making use of more than 2-4C then, so we should not go beyond that. What would have happened if CPU manufacturers had followed that advice? We'd be stuck at 2-4C. And the SW you say nowadays make use of 8-16C would never have been developed.

Same situation now. Just that the limit is claimed (by some) to be 8-16C instead of 2-4C.

So we need either the chicken or egg to progress, so we get more than 8-16C on standard desktop CPUs. Then SW will follow to make use of those additional cores.

Your post is way too simplistic for real life.

1) Some tasks, no matter what for all of the foreseeable future, cannot be separated into multiple cores. The classic example is pregnancy. Suppose the task is to make one and only one baby from start to finish. One couple can have a child in roughly 9 months. It does not matter how many couples you throw at the project, it will still take ~9 months (assuming there isn't already a pregnancy in the group which violates the rules of this thought example). There is no chicken and egg in these types of tasks. No possible amount of cores can do it any faster than a single fast core.

2) Other tasks can use many cores very easily. Suppose your task is to repopulate the Earth. One couple isn't going to do it quickly. The more couples you throw at the task the faster it will get done. Prime number searches are great examples. One core is totally independent from the next core. Just throw as many cores at it as possible and you will get a prime number sooner.

But, then you run into a physics limit. Take a given amount of power that you are willing to use for a type of chip and keep dividing that power into more and more and more cores. Eventually, you reach the point that no cores have enough power to do the work. So you can't push #2 too fast. This isn't a chicken and the egg problem either. You need to add cores as technology progresses enough to get more done with less power per core.

 

[LightningZ71]

I think that was the point of Bartlett Lake.

Maybe, though it was explicitly mentioned for edge/embedded computing. It would do very little for many of the benches that Phoronix ran.

 

[alcoholbob]

40%? This is some good MLID level content.

 

[OneEng2]

Also Intel's plan to sell Big Cache Version now people would definitely buy the 52 Core version

OK, so the contention is that people will buy a processor with lots of cores IF you also pack a bunch of cache on it so it runs fast on ST or low thread MT sensitive applications?

So it isn't the high core count they are buying, its the low thread count performance ..... and they only buy it because you don't offer the extra cache in the lower core count product so you can artificially charge more for the higher core count product?

Seems like a recipe for a major loss of revenue when AMD counters with a 12c24t X3D that equals or surpasses the monster of silicon part from Intel at a fraction of the price.

After reading the Phoronix review of the Epyc 4005, I have to wonder if Intel's dual CPU chiplets part is more targeted at being more competitive in the Entry level server/low end workstation market? The current offering is Raptor Lake with the e-cores disabled against AMD 16 core beasts. Maybe they will do a Nova lake 16 P-core part for that market now?

E Cores "mont based" are horrible at most server loads. Seems like they would need an all P core based product to compete, not simply an 8P+16E CCD. Those P cores would need to support a 512bit AVX data path and SMT to be competitive with the 4005 I believe.

CPUs with more cores need SW that can use those additional cores. And SW that can make use of more cores need CPUs with more cores.

Your claim is that we're currently in a state where (some) SW can use 8C to 16C, but not much beyond that. Now rewind to the 4C area. Similarly some claimed that SW was not making use of more than 2-4C then, so we should not go beyond that. What would have happened if CPU manufacturers had followed that advice? We'd be stuck at 2-4C. And the SW you say nowadays make use of 8-16C would never have been developed.

I can't speak for everyone; however, my claim is that the biggest demand for "more cores" is not in the desktop or laptop market, but rather workstation and data center.

In desktop and laptop markets, the vast majority of applications work best with high ST performance chips with a modest number of cores (8-16) and that low latency memory access through large 3D cache acutally does much more for a consumer here than more cores.

Furthermore, for the situations where there is an appetite for all the cores you can throw at the problem, you ALSO need tons of memory bandwidth beyond what 2 channels can provide (ie, a server/workstation with up to 16 channels of memory to feed it).

No one said that no programs (even on the desktop and laptop) do not benefit from more cores, only that it is a small minority of programs .... that only a small part of the desktop/laptop market users actually use.

 

[reb0rn]

This is so borring we do not need more cores for desktop while mobile phones have same.... will you ppl just stop it, if you do not need it and use PC just for gaming be it, most of us do not

 

[igor_kavinski]

Seems like a recipe for a major loss of revenue when AMD counters with a 12c24t X3D that equals or surpasses the monster of silicon part from Intel at a fraction of the price.

If Intel's large cache slice isn't a victim cache like on the Ryzen, it may end up being useful in a lot more workloads than just games. That's the hope, anyway.

 

[adroc_thurston]

If Intel's large cache slice isn't a victim cache like on the Ryzen

They've been NINE since TGL in client (and SKX in server).

 

[igor_kavinski]

1) Some tasks, no matter what for all of the foreseeable future, cannot be separated into multiple cores. The classic example is pregnancy. Suppose the task is to make one and only one baby from start to finish. One couple can have a child in roughly 9 months. It does not matter how many couples you throw at the project, it will still take ~9 months (assuming there isn't already a pregnancy in the group which violates the rules of this thought example). There is no chicken and egg in these types of tasks. No possible amount of cores can do it any faster than a single fast core.

The easy solution to that is to become a power user (run multiple core hungry programs at once to maximize multicore throughput). People who don't multitask heavily will rarely, if ever, feel the need for anything more than 16 threads.

 

[igor_kavinski]

They've been NINE since TGL in client (and SKX in server).

They have to do something better than AMD rather than just mimic them. Their downfall has largely been due to trying to catch up to AMD. They should've focused on their strengths (they must've those, right???).

 

[igor_kavinski]

Spoiler: By the way, Intel is making GREAT progress!

Lifted from here:

Log in

www.overclock.net

 

[adroc_thurston]

They have to do something better than AMD rather than just mimic them.

They're mimicking them even harder in server.

Their downfall has largely been due to trying to catch up to AMD

no they just couldn't execute.

 

[igor_kavinski]

no they just couldn't execute.

Because they tried to do chiplets. They have their own fabs. Arrow Lake should've been monolithic.

 

[adroc_thurston]

Because they tried to do chiplets

With advanced packaging. Really cool.

They have their own fabs.

Yeah that's a double-edged sword.

Arrow Lake should've been monolithic.

Would've not changed much.

 

[igor_kavinski]

Would've not changed much.

How so? Stock RAM latency would've been <70ns or even lower with DDR5-9000 instead of the current >85 ns.

 

[adroc_thurston]

Stock RAM latency would've been <70ns or even lower with DDR5-9000 instead of the current >85 ns.

Uh, nope.
IMC wouldn't be on the ring in any case so you're out of luck.
Also unloaded memory latency is an absolutely piss poor metric, stop using it.

 

[alcoholbob]

How so? Stock RAM latency would've been <70ns or even lower with DDR5-9000 instead of the current >85 ns.

The AIDA64 latency doesn’t really explain why Arrow Lake is so bad at gaming, because they barely get any gaming improvement going from 90ns to 60ns or even sub-60 after tuning. A 60ns Raptor Lake build is still a good 20%+ faster than a 60ns 285K build in CPU-bound gaming situations. It’s definitely a confluence of multiple bottlenecks going on.