Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Thunder 57]

Ok so you are saying one of the Chief architects of x86 of his time is lying that's pretty bold of you

Yea, it's complete junk. I don't buy it.

 

[511]

Yea, it's complete junk. I don't buy it.

you do you than

 

[Abwx]

Ok so you are saying one of the Chief architects of x86 of his time is lying that's pretty bold of you

He s lying because the P4 started with 55M transistors and got to 125M later.

 

[511]

He s lying because the P4 started with 55M transistors and got to 125M later.

OK, but was the 64bit such a massive increase in xtor count?

 

[Nothingness]

Yea, it's complete junk. I don't buy it.

Do you really think a well known designer as Bob Colwell would make such a blatant lie? I know some people make huge claims because they want to see their name all over Internet. But I see no reason to believe you over him, what evidence he's lying do you have? BTW he doesn't claim their 64-bit extension was the same as what AMD designed; they might just have paved the way to implement what AMD defined which might have helped them quickly add support. Note I use conditional, I'm not 100% confident he's not lying, but I see no reason not to fully dismiss his claim.

 

[Abwx]

OK, but was the 64bit such a massive increase in xtor count?

x64, pipeline depth, HT and 1MB cache + SSE3.

 

[Nothingness]

He s lying because the P4 started with 55M transistors and got to 125M later.

Parts of a design can be removed before going into synthesis. Your claim proves nothing at all

 

[Abwx]

Parts of a design can be removed before going into synthesis. Your claim proves nothing at all

It existed only on paper, do you believe that 50% of the die was disabled.?

 

[511]

It existed only on paper, do you believe that 50% of the die was disabled.?

maybe he is referring to the 125 million xtor Pentium he would surely know more than most of us considering design are worked few years before release.

 

[Abwx]

maybe he is referring to the 125 million xtor Pentium he would surely know more than most of us.

125M was precisely with X64 and it was a different design than the 55M one since they increased the pipeline stages from 23 to 31.

 

[Nothingness]

It existed only on paper,

You're inventing things with exactly nothing to back your claim.

do you believe that 50% of the die was disabled.?

I'm not saying parts of the die were disabled. I'm saying parts of the design might have been removed before doing synthesis. And if you don't know what the means, please take the time to look up what synthesis and back-end in general means.

 

[Abwx]

You're inventing things with exactly nothing to back your claim.


I'm not saying parts of the die were disabled. I'm saying parts of the design might have been removed before doing synthesis. And if you don't know what the means, please take the time to look up what synthesis and back-end in general means.

He said that his x64 propositions were discarded, yet they still implemented them
to better being fused off.?

That s total bs.

 

[511]

well AMD's Architects seems to believe it

https://twitter.com/x/status/1847292719254630721

 

[Nothingness]

He said that his x64 propositions were discarded, yet they still implemented them
to better being fused off.?

That s total bs.

Again, they might have implemented them and didn't enable them before going to synthesis. That's it. It's also possible that full validation wasn't done and would have delayed product release anyway.
If you had any experience in CPU design or software development, you'd know that lots of costly and working features are done that don't make it into the final product.

 

[Abwx]

well AMD's Architects seems to believe it

https://twitter.com/x/status/1847292719254630721

They are taking it face value, they dont realise that he s lying.

Again, they might have implemented them and didn't enable them before going to synthesis. That's it.
If you had any experience in design or software development, you'd know that lots of costly and working features are done that don't make it into the final product.

He said "fused off", wich mean being present in the die, you are just inventing excuses for a patented mythomaniac.

 

[511]

They are taking it face value, they dont realise that he s lying.



He said "fused off", wich mean being present in the die, you are just inventing excuses for a patented mythomaniac.

i just checked there are so many variants of Pentium 4 i am confused he may be telling the truth cause Intel has like 2-3 designs in parallel so the one he is referring to and the one that launched with 64 bit were the same.l

 

[Nothingness]

He said "fused off", wich mean being present in the die, you are just inventing excuses.

Again proving your total lack of experience on the subject. Words are being overused even by experts. I've heard several CPU designers in my team calling things fused off despite them being compeletely removed from the final steps of the design process. But yeah keep digging.

BTW your comparison of the number of transistors is utterly wrong. The differences beween Northwood and Prescott were far beyond the addition of x86-64: larger caches, process change, massive changes in the uarch. Add to that it's very possible that the initial implementation of 64-bit was less massive and intrusive than what AMD defined, and you have nothing to sustain your claim.

Again I'm not saying what Bob says is true. But the choice between a known designer and random Joe on Anandtech, in the absence of any evidence, is quickly made.

 

[Abwx]

lBut the choice between a known designer and random Joe on Anandtech, in the absence of any evidence, is quickly made.

LOL, prove that you have no argument, and btw rear view mirror man is also a chip architect...

 

[Win2012R2]

But the choice between a known designer and random Joe on Anandtech, in the absence of any evidence, is quickly made

Bob's story sounds true to me even without his credibility because it's exactly the kind of thing that big corpo like Intel would do (avoid competition with their other premium product), plus people in the know would know for certain, so for him to state it publicly would be totally idiotic to lie, nothing to gain - reputation to lose.

 

[Doug S]

100% fake. There was absolutely no 64 bit in the P4 until it needed it. I cannot believe I read such stupidity. His 64 bit just happened to be the same as AMD's? What a fool. Totally worthless fake chump. Have I made my opinion clear?

Hans DeVries did an article about Intel's "hidden" 64 bit instructions back in the day. It was pretty well known at the time. Sorry your argument is bs, you're the fool and totally worthless fake chump here.

 

[Abwx]

Hans DeVries did an article about Intel's "hidden" 64 bit instructions back in the day. It was pretty well known at the time. Sorry your argument is bs, you're the fool and totally worthless fake chump here.

His only article is this one, about a rumour...

The Yamhill rumor

Just to start with the rumor first: The 64 bit Yamhill extension is supposed to be Intel's answer to AMD's Hammer family. One can imagine that the Pentium Architects are thankful to AMD for extending the x86 architecture to 64 bit. An architecture that was supposed to reach it's end of life stage with the introduction of Itanium and it's descendents. Hammer however is up and running now, outperforming the fastest members of the Itanium Family at least in integer performance. Intel management has to make U-turns ones in while, like with their Rambus-only policy lately​

Chip Architect: Intel's Prescott Prospects

 

[poke01]

This has gone way past SIMD now. Can we get back on topic or else make a new thread with regards to who made the first x86 64-bit CPU

 

[OneEng2]

It has Y cruncher in the mix with AVX-512 when NVL will get AVX-512 there would be a change in it if in handbrake they are using SVT-AV1 it also supports AVX-512 .

It is my understanding that only the DC versions of Intel processors will be getting AVX-512.... and that isn't even true since I believe Intel is pushing AVX10 to unify their 512 and 256 bit instruction vectors across P and E cores. Still, you are correct that should Nova Lake include AVX10, and should people recompile to support this instruction set, things would look better for Intel in some of these benchmarks; however, I still believe Zen 6 will dominate due to full width AVX512 support across all cores at full speed. Additionally, Tom's benchmarks also included CB24 which is currently quite bandwidth limited. Zen 6 is likely to make inroads on CB24 which Zen 5 currently gets beaten badly by Arrow Lake in. This will balance things out a little I think.

I am guessing that Zen 6 still dominates MT on a per core basis since it includes SMT on every core. I wouldn't be surprised if a single Zen 6 core is equal to 1.5 Nova Lake cores. We will see I guess.

THe SKU can be but not limited to

• 8+16+4
• 2*(8+16)+4
• 2*(4+8)+4
• 4+8+4
• 4+0+4

the 8+16 Tile is N2 and the 4+8+4/4+0 tile is 18AP and the common SoC tile is shared across all the SKUs.

So we have Nova Lake variants of:

• 28c
• 52c
• 28c (different flavor)
• 8c

... against a lineup of Zen 6 having at least:

• 12c/24t
• 24c/48t

Also, I wonder about the 4 LP cores. Seems like these will do much more for marketing than they do for benchmarks. So for benchmark purposes perhaps it is more accurate to say Nova Lake looks like:

• 24c
• 48c
• 24c (different flavor)
• 4c

Still, at 1.5:1, the 24c Zen 6 will still only be able to do MT of 36 Nova Lake cores giving the big Nova Lake part a commanding lead in MT ..... assuming it does not become bandwidth starved.

In automotive, I have always mused that an internal combustion engine is really just an air pump. The more air you can get it to move, the more power it creates.

Processors aren't that different IMO. You have to move memory in and out to do work. The more cylinders you have (cores) the wider the air intake and exhaust needs to be to feed it (memory bandwidth).

 

[511]

It is my understanding that only the DC versions of Intel processors will be getting AVX-512.... and that isn't even true since I believe Intel is pushing AVX10 to unify their 512 and 256 bit instruction vectors across P and E cores. Still, you are correct that should Nova Lake include AVX10, and should people recompile to support this instruction set, things would look better for Intel in some of these benchmarks; however, I still believe Zen 6 will dominate due to full width AVX512 support across all cores at full speed. Additionally, Tom's benchmarks also included CB24 which is currently quite bandwidth limited. Zen 6 is likely to make inroads on CB24 which Zen 5 currently gets beaten badly by Arrow Lake in. This will balance things out a little I think.

Intel published updated AVX 10.2 Spec In January supporting only 512 bit vector that means they will also support AVX-512 P cores have Full AVX-512 and E cores will also gain this.

I am guessing that Zen 6 still dominates MT on a per core basis since it includes SMT on every core. I wouldn't be surprised if a single Zen 6 core is equal to 1.5 Nova Lake cores. We will see I guess.

Nova Lake core is based on P+E it's not a single core 😅.

So we have Nova Lake variants of:

• 28c
• 52c
• 28c (different flavor)
• 8c

... against a lineup of Zen 6 having at least:

• 12c/24t
• 24c/48t

Also, I wonder about the 4 LP cores. Seems like these will do much more for marketing than they do for benchmarks. So for benchmark purposes perhaps it is more accurate to say Nova Lake looks like:

These are for mainly battery life and idle power consumption since they are using unified SoC it would also mean a lot better better life on Hx-sku..

 

[Darkmont]

1) I personally don't see the 52 core Nova Lake in the general desktop and laptop markets. That will likely be the single chip 26 core Nova Lake. To me, the 52 core is intended for the workstation class.
2) You already know DDR6 prices? If so, please inform us. Since it is 4 channels within the same memory module, there could be fewer motherboard parts needed.

It's 4 16-bit channels. They split the channel size to keep the cache line 64 bits and more parallelism. Also 17.6 Gbps is the preliminary top speed not the introductory one.