Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Page 727 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Tigerick

Senior member
Apr 1, 2022
789
757
106
PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



LNL-MX.png

Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)



Clockspeed.png
 

Attachments

  • PantherLake.png
    PantherLake.png
    283.5 KB · Views: 24,025
  • LNL.png
    LNL.png
    881.8 KB · Views: 25,517
Last edited:

KompuKare

Golden Member
Jul 28, 2009
1,227
1,591
136
For Zen6 ISA feature best I could find is this post
Nevermind software developers, anyone working on AVX/AMX at Intel/AMD/VIA needs to feature table big enough to cover a whole wall just to know what they themself support. Software developers have it even harder as that whole-wall table really needs to be 3D with a feature checkbox for each subset, each vendor and each vendors various CPUs.

Plenty of Schadenfreude to go around for Intel as their decades of segmentation is entirely on them. That plus their near endless fragmentation means Intel really have painted into a corner. A 3D or 4D corner, that is!

As for fragmentation and standards, well I feel the xkcd carton on standards is obligatory here (surprised nobody has posted it yet, actually):
8wZAvAJ.png
 

alcoholbob

Diamond Member
May 24, 2005
6,380
449
126
View attachment 114045
CN source

It's a nice improvement, but even with all this it's still slower than a stock 14900K, considering some youtubers were running 4.3GHz ring with delided 285Ks, maxed tuned with direct die cooling and still couldn't beat a stock 14900K with same speed RAM. It's never going to catch up to the last gen. Just hope Intel doesn't fall even further behind before Nova Lake launches in 2027.
 
Last edited:

511

Diamond Member
Jul 12, 2024
3,458
3,335
106
Added 4 more cores, newer arch, higher clocks and is on N3E. PTL-H is going to be a great SoC for laptops.
also
> Beefed Up Chadmont
> No Tiling issues
> Good Low Power Island (not just meh)
Cons
> Meh P cores again afaik
> MoP missing not as low power vs LNL

My expectations
Also I don't know whether it will have PMIC support or not
 
Last edited:
  • Like
Reactions: DKR

Philste

Senior member
Oct 13, 2023
296
474
96
No profanity allowed in Tech, which includes masking letters that make it obvious to what that word is.
It's actually impressive given that bandwidth doesn't grow on trees.
Because Intel for some reason still doesn't care and just puts enough cache in there to make it work even if it takes space. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
 
Last edited:

511

Diamond Member
Jul 12, 2024
3,458
3,335
106
Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
8 MB SLC is just not for the iGPU though it has many other uses
 

511

Diamond Member
Jul 12, 2024
3,458
3,335
106
it does not.
I am not sure cause MTL-U has optional 2 PMIC Power Management I would not be surprised if PTL-U end up having this 2 PMICs are not costly w.r.t to BOM if we are allowed to diversify
it's all goodenough already.
Yeah hoping it matches M4 Pro (in MT ar least) and ST between M3/M4 that would make it damm good
 
Last edited:
  • Like
Reactions: DKR

DavidC1

Golden Member
Dec 29, 2023
1,720
2,794
96
Because Intel for some reason still doesn't care and just puts enough cache in there to make it work. Strix is still sitting at 2MB L2 for iGPU? LNL has 8MB L2 and option to use that 8MB SLC. I bet PTL-H/P has at least 16MB inside that iGPU.
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.
> Beefed Up Chadmont
> Meh P cores again afaik
3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
 

OneEng2

Senior member
Sep 19, 2022
746
997
106
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
I think the P Cores are most hamstrung by the ring bus latency ..... at least that is my theory ;).
 

511

Diamond Member
Jul 12, 2024
3,458
3,335
106
I wouldn't put much stock on LNL's SLC. It's so slow that the Arrowlake's SKT is almost 25% faster per clock. It's SRAM cache but performs like DRAM system memory.

3-5% for Darkmont and 8-10% for P cores(rumor), so P will fare a bit better comparatively.
We will see I have heard same improvements for both P and E of 5-8%