Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[jdubs03]

But that's the thing, they were able to gain 15% because they're starting from further behind. There's always headroom when you're further behind. Apple increased performance by 70% between A8 and A9, precisely because they were well behind on frequency and had a lot more low hanging fruit to grab for IPC. They're on the top of the IPC heap, so it will be harder for them to increase IPC by x% than it is for someone else who is 20% behind them in IPC.

Yeah you’ve got a point there. I was just thinking of the chart ARM presented with their gen to gen IPC gains increasing from their previous 10% in the previous years to the 15% this year. Perhaps it’ll be an anomaly.

 

[poke01]

Intel got a 9% improvement on their P core but I feel like once they move to their own nodes, the P core will see higher increases.

18A is a more advanced than N3B, so let’s see.

 

[Hulk]

Intel got a 9% improvement on their P core but I feel like once they move to their own nodes, the P core will see higher increases.

18A is a more advanced than N3B, so let’s see.

Are you thinking they will be able to increase frequency much beyond the current 5.5GHz/5.7GHz MT/ST speeds of Arrow Lake or that there will be an increased transistor budget that will allow for higher IPC, or a combination of both?

 

[igor_kavinski]

Who would want to buy this dud if its a one-and-done socket?

I've got serious doubts about that because why would ASROCK go to the trouble of putting a dropdown option in memory QVL unless they know that Core Ultra 300 series is gonna be supported on Z890 too?

 

[DavidC1]

Anybody know who came up with micro-ops and when? Saved x86 I would think?

Yea except:

https://www.realworldtech.com/silvermont/

Like its predecessor, Silvermont focuses on decoding and issuing x86 instructions into the back-end, rather than converting them into µops.

Intel's Atom Architecture: The Journey Begins

www.anandtech.com

The E cores are a totally different path from the P core lineup, and the divergence starts all the way back to the original Pentium.

@poke01 Hulk, he probably means architecturally because we aren't gonna get much higher than 6GHz.

 

[poke01]

Are you thinking they will be able to increase frequency much beyond the current 5.5GHz/5.7GHz MT/ST speeds of Arrow Lake or that there will be an increased transistor budget that will allow for higher IPC, or a combination of both?

Like David1C mentioned I mean architecturally.

 

[511]

Here are Arrow lake dimensions

https://twitter.com/x/status/1847791758890922005

https://twitter.com/x/status/1847962186963939373

 

[Hitman928]

Here are Arrow lake dimensions

https://twitter.com/x/status/1847791758890922005

https://twitter.com/x/status/1847962186963939373

That’s significantly bigger than some were predicting. I eyeballed 100 mm2 for the CPU tile but still underestimated a little bit. Definitely not cheap to make but shouldn’t be crazy expensive. Plenty of margin for retail, but not sure how much they’ll make with OEM partners.

 

[DavidC1]

That’s significantly bigger than some were predicting. I eyeballed 100 mm2 for the CPU tile but still underestimated a little bit. Definitely not cheap to make but shouldn’t be crazy expensive. Plenty of margin for retail, but not sure how much they’ll make with OEM partners.

As you can see Meteorlake based tile design has too many separations.

Having the IO and the SoC separate is a waste. Not an insignificant portion of that IO die will be just to connect with the rest. And such redundancies exist elsewhere. Like Intel said, moving to two tiles in Emerald Rapids meant at the same die size they were able to triple the amount of L3 cache on the die.

With really small GPUs setups like in desktops, the GPU could be combined with the compute tile, reducing waste further.

In the Sandy Bridge days they were basically plopping out 100mm2 Core i3 and under dies and it was super cheap to make. The cost will surely be higher with Arrowlake.

 

[csbin]

Cinebench R23 MT: 42286
Cinebench 2024 MT: 2355

https://twitter.com/x/status/1848243780186698099

 

[alcoholbob]

So a little more power efficient than Raptor Lake (maybe 20%?), but still less power efficient than Zen 5 while having a node advantage. I guess the only interesting thing left is what is the overclocking headroom on the e-cores to see if it can actually be the undisputed multi-core champion.

Jays2cents claims almost 1GHz headroom on the 285K's e-cores in his recent video which would be pretty crazy if you could get the e-cores up to something like 5.3-5.4GHz range - assuming he didn't misspeak.

 

[DavidC1]

Cinebench R23 MT: 42286
Cinebench 2024 MT: 2355

The E cores are clocked 200MHz higher than the top default Turbo frequency.

@alcoholbob I thought one tweet said 100MHz for P and 200MHz for E?

 

[poke01]

Jay is wrong, it’s up to 300MHz. Not almost 1GHz.

 

[Hougy]

Northwood-B and -C worked out well enough that they thought they could continue getting away with it. Plus keep in mind that originally Netburst was a big scheme to justify RDRAM in desktops. They had good reasons to push such a design.



I don't think anyone could have predicted an actual performance regression in ST out of Arrow Lake. Even Intel's most pessimistic slides showed +5%. That might have been on a fictional version of 20a that we never saw. N3B does not seem to be the right node for Arrow Lake. Also keep in mind that Intel may not have as much experience or skill in utilizing TSMC nodes as their primary competitor...

Why is Intel releasing an N3B chip half an year after Apple had already moved to N3E, which is much better?

 

[Det0x]

Jay is wrong, it’s up to 300MHz. Not almost 1GHz.

Indeed

 

[Gideon]

Honestly, if the densely packed E-cores can already reach up to 4.9 GHz, I struggle to see the reason for classic P cores for most future client SKUs (unless Cougar Cove is a much bigger bump in IPC than Lion Cove).

I'm pretty sure, that it would be possible to make "performance versions" of the Skymont successor, that would have more cache and be higher clocked (low 5Ghz range), trading a bit of area for clock speed, sorta the reverse of Zen 5c.

It doesn't make that much sense still in the context of Lion Cove vs Skymont, but if Intel can continue to deliver decent E-core IPC bumps in the future, it might already make sense with the next gen E-core.

 

[coercitiv]

Jay is wrong, it’s up to 300MHz. Not almost 1GHz.

He made it sound as if Intel told him that. Then again, the entire video feels like an Intel commercial where they get to throw the mobo makers under the bus while Jay is driving.

I expect the E cores to have better OC potential than the P cores because Intel will bin for P frequency. The E core bin would have to be a wider net, and will probably have higher variance (hence the higher OC potential).

 

[SiliconFly]

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[SiliconFly]

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[SiliconFly]

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[poke01]

https://twitter.com/x/status/1848279194578428319

The ring frequency and the N3B node holding it back and the MTL tile architecture. At least it doesn’t disintegrate itself, progress. The Intel way.

 

[SiliconFly]

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[SiliconFly]

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[Abwx]

Cool! Thats higher ST than 9950X.

Because CB is specificaly optimised for Intel, for instance the 9950X has only 5-6% better IPC than the 13900K in CB R23 ST but is 12-15% better in ST for all other renderers like Corona, Blender and Vray.

An average of those 4 scores would put the 9950X at roughly 10-12% better IPC than the 13900K and above the 285K wich btw look like some N3 revisited RPL KS.

 

[cannedlake240]

The E core is set to replace the P core very soon (probably 2026 or 2027).

Lol what?