Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[DavidC1]

It saves Intel money to go hybrid obviously but its not that much in the grand scheme of things. A cluster of 4 E cores is better at a specific task, multi core. If intel had to do 16 P cores, they could with make that CPU with like a 15-20% increase in die size compared to their current 8+16 situation, all 16 cores will have fat caches too compared to E cores where the cache is shared which limits their performance when loaded, they can also then enable AVX512 too.

No one thinks 15-20% is a trivial increase, not to mention the power consumption issue.

It'll especially matter in the 2+8 segment where they are moving dozens of millions of units.

On paper, 16 E cores with ~90% the IPC of Zen 5 should blow 8 Zen 5 cores out of the water but ARL muli threaded will probably be about even.

Because Zen 5 also clocks higher and has SMT.

 

[poke01]

https://twitter.com/x/status/1847496182823555576

It seems OC is weak on the 285k

 

[alcoholbob]

https://twitter.com/x/status/1847496182823555576

It seems OC is weak on the 285k

Depends if it's just the single core boost that's gimped or if its the all-core. I mean a "+100" meaning 5.8 is the cap, but if it results in up to 5.8GHz all-core then might actually be interesting since it would be +300Mhz to all core boost.

 

[Henry swagger]

Stephen's team are taking the apple approach in core design.. the unified core needs to have big ipc because apple is the king in efficiency and ipc

 

[dttprofessor]

Stephen's team are taking the apple approach in core design.. the unified core needs to have big ipc because apple is the king in efficiency and ipc

The key is next 30%+ ipc improve for ecore, when ?

 

[Henry swagger]

The key is next 30%+ ipc improve for ecore, when ?

Arctic wolf if rumours are true.. but if the m5 has 25+ ipc they.ll be behind apple again.. they need 50+ ipc lol

 

[Magio]

Arctic wolf if rumours are true.. but if the m5 has 25+ ipc they.ll be behind apple again.. they need 50+ ipc lol

Apple's P core hasn't had an 10=% gen-on-gen IPC increase since 2019, before they even launched the M series. The M4 P core is the biggest increase they've had since and that's 8%, it's ludicrous to suggest a 25% increase in M5 at this stage.

Also people have got to stop boiling everything down to IPC. For one comparison of IPCs across ISAs is a bit skewed, but more importantly what matters isn't just IPC but how the core clocks, its power characteristics, its range of operation, its perf per watt/per area, ... Skymont is already very good at some of that (PPA/W especially at low power) but it doesn't yet scale well to higher power/clocks.

I'll take a purely ARM example: Oryon and Cortex X4 have basically the same IPC, yet X4 is a steaming pile compared to Oryon in every real world scenario one can think of. IPC figures from here, in the last columns.

 

[SiliconFly]

.

 

[DrMrLordX]

In the video he says he implies the core to be widely used. It however ended up being used in just two products - Lakefield, which is basically discarded from the start, and Snow Ridge, an Edge SoC, which has no Gracemont based successor despite having a roadmap.

Tremont also wound up in Jasper Lake, Parker Ridge, and Elkhart Lake. Interestingly enough, Snow Ridge isn't even mentioned on the Wikipedia page:

Tremont (microarchitecture) - Wikipedia

en.wikipedia.org

Exist's take is that the P core team is looking to kill the Unified Core team.

That seems counterproductive.

 

[SiliconFly]

.

 

[511]

https://twitter.com/x/status/1847595575161569633

 

[Josh128]

Depends if it's just the single core boost that's gimped or if its the all-core. I mean a "+100" meaning 5.8 is the cap, but if it results in up to 5.8GHz all-core then might actually be interesting since it would be +300Mhz to all core boost.

Dready Bear just refuses to give up, lol. I think the "I hope someone has a better sample" part of the tweet is a pretty good indicator that this does not indicate 5.8GHz all core on P cores. That and the fact that if the chip could all-core P cores to 5.8GHz, theres no way Intel would have limited ST boost to 5.7GHz. Lets come back down to earth for just a minute please.

 

[OneEng2]

They want to win back server, and nobody running servers wants to deal with heterogeneous architectures.

Fair point, but the current releases have specific products for P for only and E Code only.

I think Nvidia AI chips are specialized as well.

Intel could target a specific single vertical in D with a homogeneous design.

 

[511]

https://twitter.com/x/status/1847655725381857719

 

[SiliconFly]

.

 

[9949asd]

https://twitter.com/x/status/1847655725381857719

The core performance of ARL is good, just the gaming is kind of embarrassing. Now ARL feels really like zen2 back in the day.

 

[csbin]

9950X@220W

https://twitter.com/x/status/1847662406593630691

 

[Hitman928]

That looks phenomenal. Faster than I expected and faster than 9950X too. Sure it isn't overclocked or anything?

 

[cebri1]

https://twitter.com/x/status/1847655725381857719

Pretty good result. A tad more than what I expected.

 

[Hulk]

I wish people would show frequency when they show HWinfo.

 

[MS_AT]

according go Huang, APX will give a 5% increase in performance

I guess there are caveats. Do you have full quote?

The branch MPKI tests the ability of the branch predictor to predict instructions, so anything after that will have to be measured using a different metric, such as "IPC". Skymont is simply better than Lion Cove here.

From where are you getting this?

It's only slow because it's the LNL version with the dog slow SLC cache.

Accuracy of branch prediction is one thing, latency is another, though I am not sure how well Skymont does here against Lion

 

[DavidC1]

Accuracy of branch prediction is one thing, latency is another, though I am not sure how well Skymont does here against Lion

Pretty well I would add, since Lion Cove's 9% gain is a combined figure and FP should benefit from the added units, meaning Integer gains are quite close to Skymont.

Also people have got to stop boiling everything down to IPC.

What do you mean by "IPC across different ISAs"? This is why I dislike that term. It gets people confused. When people say "IPC" they refer to performance per clock, something that doesn't matter whether it's ARM or x86.

The ARM competition uses fraction of the power to achieve performance. The focus does matter.

Also if this was 15 years ago where process scaling was easy and brought great gains, and clocks were lower, then you'd be in tune with time, because the gap between a 10 stage CPU and 20 stage CPU would have been greater.

However we have Apple and ARM both clocking over 4GHz. While the top end chip that degrades to achieve performance is at 6GHz. The desktop chips need to lower frequency in all other aspects. The fabric frequency is low, and the L3 cache isn't full speed either.
-They lose performance due to long pipelines
-They lose performance due to needing to relax cache latencies
-They lose performance because fabric/L3 can't clock at CPU core speeds.

All that for ~35% clocks and massive core power.

 

[OneEng2]

Well, there is IPC, and then there is single core performance, and then there is multi-core performance, and then there is thermally limited performance.... and then there is the workload you are talking about.

I hear lots of commentary about Skymont having nearly the IPC of Lion Cove. It is my guess that what we will find is that Skymont does some things really well, and others not so much and that Lion Cove is absolutely necessary to be competitive in a lot of workloads.

Of course, it is always possible that I am wrong.

 

[poke01]

I guess there are caveats. Do you have full quote?

https://twitter.com/x/status/1845448405969142153

Here it is

 

[poke01]

This is another.

https://twitter.com/x/status/1845438917719494886

Will 16k page support ever come to x86?