Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Joe NYC]

We need 128/256 MB eDRAM with DDR6 with RPL should be good enough 🤔

This would not perform as well as V-Cache. It would have to be on a separate chip with much higher latency and lower bandwidth.

3D V-Cache makes the cache behave almost as if it was on the same die as the cores.

 

[DavidC1]

Seems to me that battery life is pretty important in thin and light laptops.

18A may turn out better than you think with the inclusion of BSPD.

They could have backside, frontside, leftside, and rightside power delivery and it still wouldn't deliver better battery life by itself, when load power is responsible for almost nothing in bursty workloads. In fact, sometimes the burst part is so short that the CPU doesn't even reach rated Base clocks.

The thinking that process itself would deliver better battery life is an idea stuck in the early 2000's, when power management absolutely paled in comparison to today.

 

[SiliconFly]

.

 

[OneEng2]

They could have backside, frontside, leftside, and rightside power delivery and it still wouldn't deliver better battery life by itself, when load power is responsible for almost nothing in bursty workloads. In fact, sometimes the burst part is so short that the CPU doesn't even reach rated Base clocks.

The thinking that process itself would deliver better battery life is an idea stuck in the early 2000's, when power management absolutely paled in comparison to today.

Seems to me that the lead process tech is always used on the laptop market (traditionally). I don't believe that the process by itself delivers better battery life than good power management; however, I think it is naive to believe that the process isn't an important factor in low power designs.

I agree to disagree on this point.

 

[MoistOintment]

N3B does not seem to be the right node for Arrow Lake.

What node would have been the right one? Which one would have gotten comfortably past 5.7Ghz without raising power consumption beyond what it currently has?

I see ARL's mediocre results (in desktop) as:

tile latency
ring bus clock speed regression
Mediocre IPC improvements in LNC (despite a much larger transistor budget to work with)

What would a different node have fixed here?

 

[511]

What node would have been the right one? Which one would have gotten comfortably past 5.7Ghz without raising power consumption beyond what it currently has?

I see ARL's mediocre results (in desktop) as:

tile latency
ring bus clock speed regression
Mediocre IPC improvements in LNC (despite a much larger transistor budget to work with)

What would a different node have fixed here?

A good P core arch 🙂

 

[DavidC1]

Exist is saying PTL will be worse than Lunarlake for LNL's target segment. Nothing unexpected. If it looks like a duck and quacks like a duck...

David Huang on Arrowlake's regression:

“C2C doesn't matter that much, but L3 memory access latency is the most critical one besides memory latency. MTL-H vs RPL-H is like 80 cycles vs 55 cycles due to ring clock, as I tested in my Lunar Lake review.”

So tiles ain't the problem. The ring bus is. Exist says the fabric to memory is also slower. The problem being that important part of the Meteorlake team moved to Microsoft, and ARL uses the same approach. A comment is saying the acronym for the team in MS used the same abbreviated letters they were using within Intel - same team, different company.

He also agrees the P core is a politically motivated "failed team" that will try anything to try and kill internal competition.

Basically if he is right, Intel's entire success hinges on whether the terrible P core team/design dies off and hands to much better ones such as E core, or doesn't.

His assessment of the IDC P core team is pretty spectacular.
-"Lion Cove" is the worst part of Lunarlake"
-"HT was disabled since they didn't want to further delay Lion Cove which was already facing issues with development"
-"Failed team using political might to kill better ones"
-"Coasting just like in Skylake"

Seems to me that the lead process tech is always used on the laptop market (traditionally). I don't believe that the process by itself delivers better battery life than good power management; however, I think it is naive to believe that the process isn't an important factor in low power designs.

Of course it's important, just not for battery life.

 

[511]

Exist is saying PTL will be worse than Lunarlake for LNL's target segment. Nothing unexpected. If it looks like a duck and quacks like a duck...

How worse we would have to see those PMIC are something else the MoP was never that big factor

David Huang on Arrowlake's regression:

So tiles ain't the problem. The ring bus is. Exist says the fabric to memory is also slower. The problem being that important part of the Meteorlake team moved to Microsoft, and ARL uses the same approach. A comment is saying the acronym for the team in MS used the same abbreviated letters they were using within Intel - same team, different company.

that is why RingBus has OC Headroom cause they played it safe and regression in gaming

He also agrees the P core is a politically motivated "failed team" that will try anything to try and kill internal competition.

Basically if he is right, Intel's entire success hinges on whether the terrible P core team/design dies off and hands to much better ones such as E core, or doesn't.

His assessment of the IDC P core team is pretty spectacular.
-"Lion Cove" is the worst part of Lunarlake"
-"HT was disabled since they didn't want to further delay Lion Cove which was already facing issues with development"
-"Failed team using political might to kill better ones"
-"Coasting just like in Skylake"

I couldn't agree more on 1,3,4

 

[DrMrLordX]

As I wrote above I'm not challenging your assessment, I know you are very intelligent and well thought-out in your responses, so I'm thinking you have some metrics in your head and I'm curious about them?

Well as you may know, I'm not a huge fan of Geekbench. Intel has historically done very well in that benchmark versus x86 competition. If anything I was expecting GB6 1T to be one of their more-favorable benches. And yet . . .

Until we see third party reviews, it's impossible to know exactly where everything will "land". It's just that it's weird seeing it backslide in a bench that I would have expected to show Arrow Lake in a favorable light.

 

[coercitiv]

You forgot the flys.

I didn't forget. Last time I checked the flys play be the rules and engage in meaningful conversation. Disagreement is not a problem, neither is daydreaming.

Exist is saying PTL will be worse than Lunarlake for LNL's target segment. Nothing unexpected. If it looks like a duck and quacks like a duck...

David Huang on Arrowlake's regression:

So tiles ain't the problem. The ring bus is. Exist says the fabric to memory is also slower.

I'm surprised by the L3/ringbus talk. With memory access at least it made sense (from far away) as data ends up transiting at least 1 more connection before reaching the core.

I'm not sure I understood the comment about teams moving to MS, you mean they work within MS for tighter integration?

 

[poke01]

https://twitter.com/x/status/1847148619763536224

I want to see if productivity is improved. Gaming looks to be a wash, I hope there is at least a saving grace to ARL.

 

[alcoholbob]

Well if they cant even beat 12th gen they will need a refresh on the platform with faster clocks at least, otherwise the retail box versions of the chips will hardly move. Who would want to buy this dud if its a one-and-done socket?

 

[511]

Gaming wash was clear from Intel slide i want to see their Performance/efficiency claims

 

[MS_AT]

The thinking that process itself would deliver better battery life is an idea stuck in the early 2000's, when power management absolutely paled in comparison to today.

Well, Snapdragon 8 gen 1+ was a marketing name given to Snapdragon 8 gen 1 that was ported from Samsung to TSMC. This gave 15% efficiency boost iirc. Not to say chip design doesn't matter, but it is a clear example that process tech delivers better battery life for iso design so to speak

 

[Krteq]

Found this "gaming perf. preview" in 1440p Ultra details - so GPU limited mostly , but... temps are awful and min FPS are worse most of the time

Also, source is debatable

 

[coercitiv]

One thing that boggles my mind is Intel going with the "Ultra" rebranding just before MTL and ARL. Both gens bring little overall performance improvements, sometimes they even regress. The Ultra moniker is essentially wasted on them. Then again, this is the same team that thought "Intel Processor" is a good idea for a CPU name, so maybe I should just accept the weirdness. I can always find worse naming with AMDs newest mobile lineup.

 

[ShimmerBlade]

https://twitter.com/x/status/1847105605963534529

Arrow Lake delidded.

 

[João Bortolace]

Apx is comming in DMR, so NVL also?

https://twitter.com/x/status/1847192948003201365

 

[Josh128]

Some bad juju on Twitter (dont have the link) saying it will be lucky to beat 12th gen in gaming, nT will be mostly comparable to 14900K when both are unlimited power plan, and general workloads will see improvement. Someone will post it, it was by HXL9550pro I think.

 

[AcrosTinus]

Some bad juju on Twitter (dont have the link) saying it will be lucky to beat 12th gen in gaming, nT will be mostly comparable to 14900K when both are unlimited power plan, and general workloads will see improvement. Someone will post it, it was by HXL9550pro I think.

Let us wait and see.

I think the raptor lake fiasco forced Intel to be very conservative with their settings.
If the hope is real and I can restore the performance by overclocking ring, tile and memory.

 

[511]

Some bad juju on Twitter (dont have the link) saying it will be lucky to beat 12th gen in gaming, nT will be mostly comparable to 14900K when both are unlimited power plan, and general workloads will see improvement. Someone will post it, it was by HXL9550pro I think.

If someone is comparing Unlimited settings they are doing something very wrong I don't even think TSMC Silicon scales like Intel one testing should be done with default profiles shipped with Motherboards

 

[jpiniero]

One thing that boggles my mind is Intel going with the "Ultra" rebranding just before MTL and ARL. Both gens bring little overall performance improvements, sometimes they even regress. The Ultra moniker is essentially wasted on them. Then again, this is the same team that thought "Intel Processor" is a good idea for a CPU name, so maybe I should just accept the weirdness. I can always find worse naming with AMDs newest mobile lineup.

The Ultra branding is because of AI. Just be happy they didn't call it Core AI.

Yes the TOPS number on Arrow Lake-S isn't that great... but that isn't going to stop Intel, now is it?

 

[vanplayer]

Some bad juju on Twitter (dont have the link) saying it will be lucky to beat 12th gen in gaming, nT will be mostly comparable to 14900K when both are unlimited power plan, and general workloads will see improvement. Someone will post it, it was by HXL9550pro I think.

If you use Gear4 with CUDIMM, yes it would have chance to be worse than 12th gen.

TBH, the situation is worse than expected, I wonder if there's anything wrong with the BIOS or not. The things I heard these days could be described as 'disaster', when comes to gaming.

This tweet below is just one of them but not most important. Something I couldn't talk about or draw any conclusion here, I wish there's something wrong with it.

https://twitter.com/x/status/1844181769375056276

 

[OneEng2]

Well, Snapdragon 8 gen 1+ was a marketing name given to Snapdragon 8 gen 1 that was ported from Samsung to TSMC. This gave 15% efficiency boost iirc. Not to say chip design doesn't matter, but it is a clear example that process tech delivers better battery life for iso design so to speak

Clearly the process node has a clear effect on power consumption. Whew. There form a minute I thought the laws of physics had gone and changed and I had missed the memo .

 

[511]

Clearly the process node has a clear effect on power consumption. Whew. There form a minute I thought the laws of physics had gone and changed and I had missed the memo .

Let's not talk about Samsung their nodes after 14nm have been a downhill same with Intel after 14nm we had 14nm++++ or 10nm+++ it's just in like a year they ramped Intel 4/3 both are kind of same node but at least they are good