Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Hulk]

It would be ironic if Skymont ends up being the basis for the primary Intel architecture. Remember when Core evolved from the mobile corner of Intel and rose up to be the headliner?

 

[Hulk]

The quote below is from "Tech Report." Could someone elaborate on the difference between the interposer vs AMD chiplets? I'm not quite understanding.

"An interposer facilitates high-density microscopic wiring between tiles or chiplets stacked on top of it, which would otherwise not be achievable on the fiberglass substrate. This is the key difference between Intel's tile-based processor, and AMD's chiplet-based ones, which rely on the package substrate to connect the CPU complex dies (CCDs) to the I/O die (cIOD)."

 

[Hitman928]

The quote below is from "Tech Report." Could someone elaborate on the difference between the interposer vs AMD chiplets? I'm not quite understanding.

"An interposer facilitates high-density microscopic wiring between tiles or chiplets stacked on top of it, which would otherwise not be achievable on the fiberglass substrate. This is the key difference between Intel's tile-based processor, and AMD's chiplet-based ones, which rely on the package substrate to connect the CPU complex dies (CCDs) to the I/O die (cIOD)."

Chiplets and tiles are just names for the same thing. The difference is that ARL has dies on a silicon interposer and Zen 5 is on the substrate with no interposer. Using the silicon interposer allows for more dense pins and lower power inter-die signaling, but is more expensive.

 

[Hulk]

Chiplets and tiles are just names for the same thing. The difference is that ARL has dies on a silicon interposer and Zen 5 is on the substrate with no interposer. Using the silicon interposer allows for more dense pins and lower power inter-die signaling, but is more expensive.

Thanks. What is the fabrication process for the "wiring" for AMD parts?

 

[Hitman928]

Thanks. What is the fabrication process for the "wiring" for AMD parts?

It’s just the package. You can think of it like a mini motherboard.

 

[DavidC1]

"The P core" as in Core or P6 lineage, so Golden cove, LionCove...

Yes, but P = Performance and E = Efficiency.

Also the E-core slide says this: "E-core efficiency meets P core performance"

From Techpowerup:

With "Skymont" cores having such significantly higher IPC, Thread Director on "Arrow Lake-S" prioritizes all non-gaming productivity workloads to the E-cores, and upgrades threads to the P-cores only as needed. Thread Director plays a significant role in improving the processor's overall power efficiency.

Sounds similar to what they were talking about in Lunarlake. Perhaps this is the real reason for productivity efficiency improvements @coercitiv?

 

[511]

the botched skymont was good enough to reach on rimg crestmont

 

[DavidC1]

the botched skymont was good enough to reach on rimg crestmont

So the Arrowlake presentation is basically saying that changing the LLC for Skymont from the one in Lunarlake to 36MB ring is responsible for anywhere from 10-20% in Int average, and 20-50% in FP in average, when you take both C&C and David Huang's results. (C&C's results are much lower than Huang's)

It's a huge result, analogous to what AMD got with their Athlon 64 when moving from the chipset memory controller to an on-die one. AMD quoted 20% on the IMC alone.

 

[Henry swagger]

If switching allows Intel to have a much superior product, then they'll get more money over the long run, which is the point of investing.

32% Int/72% FP means there's a possibility there's less than 5% advantage for Lion Cove over Skymont, and that's with a full 3x core size difference. There's 23% top clock difference too, but not looking too impressive now.

Maybe that 5% difference can be made up simply by having the L3 cache as fast as Raptorlake? Who knows? Whatever made Lion Cove go from 14% to 9% would reasonably result in 32/72% going to 37%/75%.

If Arctic Wolf achieves another 30% general purpose gain, then we'll have a situation where Intel can claim it beats the last gen P core performance in outright performance, not just per clock.

The p core team have bern embarrassed .. skymont is way smaller but nearly same ipc

 

[Wolverine2349]

The p core team have bern embarrassed .. skymont is way smaller but nearly same ipc

Yeah how much behind in real world IPC is Skymont compared to Lion Cove?

Would Intel have just used Skymont and scrapped Lion Cove is Skymont could clock near as high.

It appears its mostly clock speed deficit holding back Skymont for nearly equaling Lion Cove performance?

 

[lopri]

Something is not adding up here. Or the chart is ambiguous as to what exactly it is displaying. Look at FI 23 and FI 24 performance.

285K is 15% faster in FI 23 and 7% slower in FI 24 compared to 14900K.
285K is 4% slower in FI 23 and 7% slower in FI 24 compared to 9950X.

Is that possible?

 

[ikjadoon]

Finally, the chart is now complete with official numbers (thanks, ASRock):

MB slots & DIMMs	Alder Lake	Raptor Lake	Raptor Lake Refresh	Arrow Lake
2-slot: 2xDIMM 1R	4800	5600	5600	6400
2-slot: 2xDIMM 2R	4800	5200	5600	6400
4-slot: 2xDIMM 1R	4400	4400	4400	5600
4-slot: 2xDIMM 2R	4400	4400	4400	5600
4-slot: 4xDIMM 1R	4000	4000	4000	4800
4-slot: 4xDIMM 2R	3600	3600	3600	4400
CAMM2	N/A	N/A	N/A	??

Slightly higher than my anticipation, with even dual-ranked 2xDIMM in 2-slot motherboards allowing the full JEDEC 6400.

12th Gen Source
13th & 14th Gen Source
ASRock 1DPC Z890 motherboard source
ASRock 2DPC Z890 motherboard source

ASRock does not follow Intel's abbreviations, but I find ASRock's more obvious.

//

This does not include OCing; some 4-slot Z890 motherboards are advertising wild 2xDIMM 1R OC speeds (surely CUDIMM & a lucky IMC).

 

[lopri]

The quote below is from "Tech Report." Could someone elaborate on the difference between the interposer vs AMD chiplets? I'm not quite understanding.

"An interposer facilitates high-density microscopic wiring between tiles or chiplets stacked on top of it, which would otherwise not be achievable on the fiberglass substrate. This is the key difference between Intel's tile-based processor, and AMD's chiplet-based ones, which rely on the package substrate to connect the CPU complex dies (CCDs) to the I/O die (cIOD)."

Here look at the die(s) shot. They communicate through another layer of silicon (interposer).

 

[DavidC1]

The quote below is from "Tech Report." Could someone elaborate on the difference between the interposer vs AMD chiplets? I'm not quite understanding.

Tech Report used to be a very reputable and big site and had lots of reviews and news. Unfortunate they died.

"An interposer facilitates high-density microscopic wiring between tiles or chiplets stacked on top of it, which would otherwise not be achievable on the fiberglass substrate. This is the key difference between Intel's tile-based processor, and AMD's chiplet-based ones, which rely on the package substrate to connect the CPU complex dies (CCDs) to the I/O die (cIOD)."

An interposer existed forever. Traditional CPUs dating wayy back used organic interposers. Like @Hitman928 says, it's basically silicon die on a PCB.

When they went chiplets/tiles though, they needed a much denser, faster interface. Since silicon is already in the nanoscale anyway, what they did is basically create another die just for communication, and that's what a silicon interposer is. The connections are in the micro scale, so it's pretty easy to make, and basic silicon wafer is dirt cheap when using for much older processes.

So basically they take that silicon interposer and embed in the CPU package. And you take your CPU die and put it on top of it, which is why they call it 2.5D. Now you have a super fast, dense connection for your chip(lets)!

 

[Hulk]

Let's see. Intel is telling us Arrow Lake Lion Cove is +9% IPC compared to Raptor Cove and Lunar Lake Lion Cove is +14% compared to Redwood Cove in Meteor Lake.

So where does this put the tile penalty in terms of IPC?

 

[511]

Let's see. Intel is telling us Arrow Lake Lion Cove is +9% IPC compared to Raptor Cove and Lunar Lake Lion Cove is +14% compared to Redwood Cove in Meteor Lake.

So where does this put the tile penalty in terms of IPC?

-5-6% 🤣

 

[Hulk]

Tech Report used to be a very reputable and big site and had lots of reviews and news. Unfortunate they died.

An interposer existed forever. Traditional CPUs dating wayy back used organic interposers. Like @Hitman928 says, it's basically silicon die on a PCB.

When they went chiplets/tiles though, they needed a much denser, faster interface. Since silicon is already in the nanoscale anyway, what they did is basically create another die just for communication, and that's what a silicon interposer is. The connections are in the micro scale, so it's pretty easy to make, and basic silicon wafer is dirt cheap when using for much older processes.

So basically they take that silicon interposer and embed in the CPU package. And you take your CPU die and put it on top of it, which is why they call it 2.5D. Now you have a super fast, dense connection for your chip(lets)!

I made a mistake. The quote was from "Tech Powerup."

 

[511]

EMIB is different from Foveros they basically put a cavity in package than put the bridge/connectivity than some processing is done after that chip are placed on top of package connected by the bridge
Detailed read

Intel’s EMIB Packaging Technology – A Deep Dive - Semiwiki

The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations. Three classes of MCP offerings have emerged: wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for...

semiwiki.com

 

[adroc_thurston]

EMIB is different from Foveros they basically put a cavity in package than put the bridge/connectivity than some processing is done after that chip are placed on top of package connected by the bridge

Yeah it's the poverty option. Worse pitch, worse signaling power at a lot lower cost and no retsize limits.

 

[Hitman928]

Tech Report used to be a very reputable and big site and had lots of reviews and news. Unfortunate they died.

An interposer existed forever. Traditional CPUs dating wayy back used organic interposers. Like @Hitman928 says, it's basically silicon die on a PCB.

When they went chiplets/tiles though, they needed a much denser, faster interface. Since silicon is already in the nanoscale anyway, what they did is basically create another die just for communication, and that's what a silicon interposer is. The connections are in the micro scale, so it's pretty easy to make, and basic silicon wafer is dirt cheap when using for much older processes.

So basically they take that silicon interposer and embed in the CPU package. And you take your CPU die and put it on top of it, which is why they call it 2.5D. Now you have a super fast, dense connection for your chip(lets)!

The interposer isn’t embedded, it sits on top. Silicon bridges are embedded.

 

[511]

Yeah it's the poverty option. Worse pitch, worse signaling power at a lot lower cost and no retsize limits.

It's poverty option but better than traditional package that is used in AMD Zen Desktop/Server processor

 

[DavidC1]

The interposer isn’t embedded, it sits on top. Silicon bridges are embedded.

Thanks for the info!

I made a mistake. The quote was from "Tech Powerup."

🤣😂

Yea TPU isn't defunct.

Let's see. Intel is telling us Arrow Lake Lion Cove is +9% IPC compared to Raptor Cove and Lunar Lake Lion Cove is +14% compared to Redwood Cove in Meteor Lake.

So where does this put the tile penalty in terms of IPC?

Wait for what they say about the ring frequency first.

 

[naukkis]

Let's see. Intel is telling us Arrow Lake Lion Cove is +9% IPC compared to Raptor Cove and Lunar Lake Lion Cove is +14% compared to Redwood Cove in Meteor Lake.

So where does this put the tile penalty in terms of IPC?

Arrowlake runs it L3 ring interconnect 1.1GHz lower speed than Raptorlake. That itself reduces L3 bandwidth and increase both L3 and memory latencies. To compensate that slow L3 they need to increase L2 capacity which will also affect performance because L2 latencies grow too. Tile penalty is very small compared to that ring deficit. Ring difference itself can be measured by running IPC comparison at Arrowlake ring frequency.

 

[alcoholbob]

Lol, so they kinda sandbagged the Skymont performance by saying 32% for the E cores and 9% for the P cores, when for Skymont it was just for Int, and for the P cores it was combined Int/FP.

I don't know why the gains got lowered from the initial 14%. Considering Lion Cove adds additional FP units too, it's very disappointing. That means Integer gains are possibly lower than 9%.

The Youtube Arrowlake video has the Intel guy basically ignoring Lion Cove and just praising Skymont. This is basically telling us what their future arch is.

Intel also bragged about 15% less die space otherwise needed to make hyper-threading work during the Lunar Lake unveil. So they had a bunch of extra die space to do something interesting for single thread performance and this is all they came up with. No wonder the E-Core team is taking over the next generation uarch.

 

[poke01]

No wonder the E-Core team is taking over the next generation uarch.

when is this arriving? Nova Lake or even later say 2027?