Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Hulk]

If ARL ST is +3% better than Raptor Lake and if frequency of Lion Cove is 5.7GHz then IPC advantage of Lion Cove over Raptor Cove will be about 8.5%. The clock regression and tile penalty is problematic as I have been posting. I don't know anything the rest of us here don't know but my intuition tells me Lion Cove in ARL will do better than 3% overall performance increase compared to Raptor Cove. I'm thinking more like 8% better than Raptor. This will be the new tiled P core baseline.

+15% MT performance would indicate Skymont running +68% IPC over Gracemont and operating at 4.6GHz. As we have been thinking Skymont will be the star of the ARL show.

 

[AcrosTinus]

If ARL ST is +3% better than Raptor Lake and if frequency of Lion Cove is 5.7GHz then IPC advantage of Lion Cove over Raptor Cove will be about 8.5%. The clock regression and tile penalty is problematic as I have been posting. I don't know anything the rest of us here don't know but my intuition tells me Lion Cove in ARL will do better than 3% overall performance increase compared to Raptor Cove. I'm thinking more like 8% better than Raptor. This will be the new tiled P core baseline.

+15% MT performance would indicate Skymont running +68% IPC over Gracemont and operating at 4.6GHz. As we have been thinking Skymont will be the star of the ARL show.

As long as I can cool that thing all core turbo with an air cooler, I'm fine. I just don't linke the changes with the W880 chipset if they are true, now with no overclocking... My W680-Ace needs a good replacement with slim SAS.

 

[deasd]

Jaykihn's Xitter post. QS would be out in October?

https://twitter.com/x/status/1810152234807627782

https://twitter.com/x/status/1810072272301957250

 

[csbin]

interesting

https://twitter.com/x/status/1810155769440121217

 

[poke01]

Jaykihn's Xitter post. QS would be out in October?

https://twitter.com/x/status/1810152234807627782

https://twitter.com/x/status/1810072272301957250

this actually makes Apple seem like they are in a different universe.

Apple on the same node family got around +18% ST uplift from M3 to M4.

Lion Cove is truly a dud and I don’t mean to heckle or belittle, it’s the truth from these results so far and yes it can improve. What this shows is that Intel needed at least 30% IPC gain from Lion Cove because clocks are stagnant.

 

[HurleyBird]

Apple on the same node family got around +18% ST uplift from M3 to M4.

At the same time, M2 and M3 both make Apple look like they're stuck in rut. And most of the increase since M1 is from clock speed, at the expense of power, and there's only so much to wring out there before you hit a wall.

 

[poke01]

M2 and M3 both make Apple look like they're stuck in rut.

Yeah, M2 to M3 wasn’t great but that was N5P to N3B. Intel’s going from Intel 7 to N3B.

And most of the increase since M1 is from clock speed, at the expense of power

Still under 10 watts per core.

and there's only so much to wring out there before you hit a wall.

True but someone has to break the wall. Wonder who it will be?

 

[DrMrLordX]

there has to be some performance per watt improvement right?

I mean they’re jumping from Intel 7 to N3B.

Edit: Those numbers are at 250w, crazy. Wtf, is Intel doing?

Oh dear, that leaked slide was optimistic. 3%/15% is even worse than 5%/20%. As to why . . . is it possible that N3B is inflicting some kind of power scaling problem? Are we going to see a situation similar to what we saw with Zen4, where power scaling past ~120W PPT didn't help performance that much?

 

[DavidC1]

Oh dear, that leaked slide was optimistic. 3%/15% is even worse than 5%/20%. As to why . . . is it possible that N3B is inflicting some kind of power scaling problem? Are we going to see a situation similar to what we saw with Zen4, where power scaling past ~120W PPT didn't help performance that much?

It's simply TSMC is more optimized for lower frequency than Intel process.

If ARL ST is +3% better than Raptor Lake and if frequency of Lion Cove is 5.7GHz then IPC advantage of Lion Cove over Raptor Cove will be about 8.5%. The clock regression and tile penalty is problematic as I have been posting. I don't know anything the rest of us here don't know but my intuition tells me Lion Cove in ARL will do better than 3% overall performance increase compared to Raptor Cove. I'm thinking more like 8% better than Raptor. This will be the new tiled P core baseline.

I don't believe in the Tile penalty anymore. "Tile Penalty" rumor is based on comparing Meteorlake, a mobile part versus Raptorlake. Geekerwan results show otherwise.

It is an ES2 so clock frequency is likely lower than 5.7GHz as in the leak here some time ago.

The people expecting some magical gains out of LNC in Arrowlake seems to be a minor version of those in denial about Zen 5 not having 40% improvement per clock.

 

[DavidC1]

this actually makes Apple seem like they are in a different universe.

Apple on the same node family got around +18% ST uplift from M3 to M4.

Lion Cove is truly a dud and I don’t mean to heckle or belittle, it’s the truth from these results so far and yes it can improve. What this shows is that Intel needed at least 30% IPC gain from Lion Cove because clocks are stagnant.

Haha. This reminds me of Presler. It was more efficient due to the 65nm process and little better but still not enough.

E core team looks like the future of x86 for now.

interesting

https://twitter.com/x/status/1810155769440121217

Yea, this wasn't like "estimates" for Raptorlake while ago when Intel said single digit gains. This leak was benchmarking data. Of course they knew how it would perform months in advance. They make the chip.

I bet since the ES2 is bit underperforming even compared to the graph, the final version will be approximately in that range. Oh, and 5.4GHz for ES2 would explain the 8.5% vs 14% expected gap in performance.

+15% MT performance would indicate Skymont running +68% IPC over Gracemont and operating at 4.6GHz. As we have been thinking Skymont will be the star of the ARL show.

68% is only for FP.

 

[coercitiv]

Who says power consumption went down?

A leak from last year referenced PL2 177W for ARL-S 8P-16E.

Intel Arrow Lake-S CPU power limits: 125W PL1, 177W PL2, 333W PL4 | igor´sLAB

Intel’s upcoming Arrow Lake-S desktop CPUs are said to be particularly efficient with power limits of 125W for the PL1, 177W for the PL2 and 333W for the short-term PL4 as the absolute upper limit for…

www.igorslab.de

Edit: Those numbers are at 250w, crazy. Wtf, is Intel doing?

Comparison had to be done @250W because that is the setting for consumer RPL. Whether ARL-S continues with the madness remains to be seen.

 

[DavidC1]

Chiplets are not free of an energy penalty though. How much? That's anyone's guess for now.

It's the Core that sucks, specifically the Lion Cove core. That means the fancy stuff like 8-wide decoders, 8x fetch, is of trivial gains, while adding ton of transistors(area and power). Same with the added so-called L0 cache, which reduces latency negligibly compared to L1 on Golden Cove.

I have a feeling based on the lower than expected performance gains, the branch prediction improvements are also fairly small on Lion Cove. There may also be non-trivial cutbacks in core resources just like Zen 5.

Of course, Skymont at 4.6GHz is being pushed out of the efficiency range as well, but at least it's providing decent MT uplift.

It makes perfect sense why the E core is about to lap them, and completely this time. The rate of innovation, changes, and new ideas from them with a single generation is equal to 3-5 generations of the P core team.

Here's another sobering conclusion about the 14% gains: Since LNC goes from 3 to 4 vector units, this means the Integer gains are even less. Probably it's 10% for Int and 18% for FP. Compares well with 30%/70% on Skymont doesn't it?

 

[AcrosTinus]

I think the overall performance of RTL-R was already more than people needed in mainstream. The only problem I have with my 13700K system and 14900K system is the power draw, I never needed an 360mm to 420mm AIO to prevent my CPU from throttling. The performance of Raptor Cove is still crazy and will remain so for at least 4 years, we only outgrew SKL 3 to 4 years ago.

Intel potentially trying to bring the beast back into the barn while giving us 10 to 15% more performance is alright by me. Look at the Zen5 GB6 leaks for the 9900, it has a 8% lead in ST to the 14700K and still loses to it in MT. That CPU here in Germany can be bought for 380 to 420 bucks.

Big performance increases are accumulative not from gen to gen, in 4 gens we will be talking(+40%ST +100% to 200% in MT) which is my upgrade cycle for both of my machines.

 

[Geddagod]

The perf/watt improvements slide...

...appears to be very interesting.
Correct me if I'm wrong, but from what I've seen, generally, large architectural updates iso node extend the perf/watt curve at the upper power range while having worse perf/watt uplifts at the lower power range, as seen here:
And also seen in how CYPC literally has worse perf/watt than SKL at lower power levels....
But node uplifts have higher perf/watt uplifts at the lower end of the power range, and lower uplifts at the higher end, as seen here:

Looking at LNC, the perf/watt uplifts seem to be greatest at lower power levels, which seems to me that the arch perf/watt uplift isn't all that amazing (maybe 10%?) and N3B is carrying them at perf/watt improvements at lower power.
I believe GLC was also perhaps a 10% uplift in perf/watt iso node, and CYPC (when it wasn't a straight up regression at low power) was also similar, but there is no actual data for this AFAIK, so this is mostly coming of interpolation based on obscure tests and guesswork.
Getting a decent perf/watt uplift from a smaller IPC uplift isn't as bad as it first sounds IMO, because that could also mean that Intel has improved the physical design or the efficiency of getting performance gains architecturally, but that's really the only silver lining one can make out of this.
Who knows. LNL isn't too far out, and this is mostly just speculation

 

[Geddagod]

E core team looks like the future of x86 for now.

TBH, the more hype I see around the E-cores, the more wary I get lol.
In some ways, the E-cores seem to be just as resource hungry as many of Intel's previous cores (for similar PPC)....
A decent bit fewer ROB entries, but also a 3x3 decoder vs a 6 wide decoder, and an 8 wide dispatch rate vs 6 for RPC, and the massive backend, though ig no uOP cache too...
And Zen 4 seems to be an even slimmer core still vs Skymont in some ways, while achieving nearly the same IPC and likely higher ST perf to boot...
Idk, I would like to see a power curve and a die shot for area before believing in the hype too much lol

 

[coercitiv]

And Zen 4 seems to be an even slimmer core still vs Skymont in some ways, while achieving nearly the same IPC and likely higher ST perf to boot...

Arguably what should be compared is Skymont vs. Zen 5C. They are contemporary cores with somewhat similar targets for efficiency.

 

[Panino Manino]

I know this isn't the topic for this, but I also think this may be the best place to ask, not wanting to create a topic just for one question that will probably go unanswered.

I was thinking about chipsets.
I know that when microprocessors where "invented" they came bundled by support chips. I imagine that with time not only some of those chips were Incorporated to the processor itself, like the one to control and manage memory, but also where consolidated into one larger chip that came to be called "chipset", exactly because it was about that "set of chips" needed to make the processor work.

Is there any place out there that tells this story?
How the "chipset" came to be? I remember that in the 1990's there was a competitive market with first party and third party chipsets.

Again, sorry for asking about this here, but seeing these future Intel chips that are integrating even more into a single chips makes me think about this. Maybe in the future there will be a motherboard with not chipsets?

 

[Ghostsonplanets]

Maybe in the future there will be a motherboard with not chipsets?

Arguably there has been no need for chipsets for years already. They're basically glorified IO extenders now.

I remember that in the 1990's there was a competitive market with first party and third party chipsets.

Until the late 2000's there was still a competitive chipset market with tons of vendors. But as soon as Intel and AMD started integrating everything into a SoC, the need for a chipset and the market for it essentially became a vestigial feature.

I think for Intel Sandy Bridge was the first true "SoC" that finally integrated everything.

 

[The Hardcard]

TBH, the more hype I see around the E-cores, the more wary I get lol.
In some ways, the E-cores seem to be just as resource hungry as many of Intel's previous cores (for similar PPC)....
A decent bit fewer ROB entries, but also a 3x3 decoder vs a 6 wide decoder, and an 8 wide dispatch rate vs 6 for RPC, and the massive backend, though ig no uOP cache too...
And Zen 4 seems to be an even slimmer core still vs Skymont in some ways, while achieving nearly the same IPC and likely higher ST perf to boot...
Idk, I would like to see a power curve and a die shot for area before believing in the hype too much lol

I think the E cores are the future of x86, but not in the sense that they will be replacing the P cores. They’re not designed for high clock, high power, top performance and don’t seem to be currently on that path.

They do look though to be able to have a tremendous amount of compute in the 3 to 4 watt range. enough to likely make Intel’s chips top competitors in mobile as well being extremely useful for desktop throughput. When I was first reading about Lakefield, the design goals seemed weird to me, but Skymont looks like it’s really going to hit home.

I think Qualcomm will be able to trudge along in the laptop market, but Skymont is looking like it’s going to kill any dreams of them dominating the laptop space. Plus, even though the four to one ratio got blown out of the water, It looks like the key to any amount huge multithreading throughput increases calls for more E cores.

But 4 to 8 P cores will be needed for the foreseeable future outside of specific markets. Snappy and gamey still need the Sons Of The P.

 

[TwistedAndy]

If ARL ST is +3% better than Raptor Lake and if frequency of Lion Cove is 5.7GHz then IPC advantage of Lion Cove over Raptor Cove will be about 8.5%. The clock regression and tile penalty is problematic as I have been posting. I don't know anything the rest of us here don't know but my intuition tells me Lion Cove in ARL will do better than 3% overall performance increase compared to Raptor Cove. I'm thinking more like 8% better than Raptor. This will be the new tiled P core baseline.

+15% MT performance would indicate Skymont running +68% IPC over Gracemont and operating at 4.6GHz. As we have been thinking Skymont will be the star of the ARL show.

Lion Cove was optimized to be more performant at lower power limits; its performance/power curve is steeper at the beginning and quickly becomes saturated. It's closer to the typical AMD Ryzen curves, where, at a certain point, there is literally no performance improvement regardless of the power limit.

It's probably related to the TSMC N3B node, which doesn't scale well at high frequencies (>5 GHz) because of the more aggressive v/f curve. As a result, we have a situation when the Lion Cove CPU is running on a lower frequency than a typical Raptor Cove core on high power levels (>200W).

 

[ondma]

If ARL ST is +3% better than Raptor Lake and if frequency of Lion Cove is 5.7GHz then IPC advantage of Lion Cove over Raptor Cove will be about 8.5%. The clock regression and tile penalty is problematic as I have been posting. I don't know anything the rest of us here don't know but my intuition tells me Lion Cove in ARL will do better than 3% overall performance increase compared to Raptor Cove. I'm thinking more like 8% better than Raptor. This will be the new tiled P core baseline.

+15% MT performance would indicate Skymont running +68% IPC over Gracemont and operating at 4.6GHz. As we have been thinking Skymont will be the star of the ARL show.

What a disaster, if the 3 to 5% ST performance improvement is true. It is even more disastrous because they supposedly gave up HT to improve single core performance. As for Skymont, I dont really care. My focus is gaming, and so far, unless something has changed that I am not aware of, the E cores do little or nothing to improve gaming. If these numbers are in fact true, Intel could be significantly behind vanilla Zen 5 in gaming, much less the V cache chips. But dont worry, Intel has a killer product for next year, right? Oh, wait, all they have is ARL-R.

 

[AcrosTinus]

What a disaster, if the 3 to 5% ST performance improvement is true. It is even more disastrous because they supposedly gave up HT to improve single core performance. As for Skymont, I dont really care. My focus is gaming, and so far, unless something has changed that I am not aware of, the E cores do little or nothing to improve gaming. If these numbers are in fact true, Intel could be significantly behind vanilla Zen 5 in gaming, much less the V cache chips. But dont worry, Intel has a killer product for next year, right? Oh, wait, all they have is ARL-R.

Vanilla Zen 5 will be behind or barely on the level of the current Raptor-Refresh (in Gaming).

 

[ondma]

Vanilla Zen 5 will be behind or barely on the level of the current Raptor-Refresh (in Gaming).

Lets not forget all the mitigations coming for RL and RL-R to mitigate the instability issues. They will be lucky to maintain parity with Zen 4, much less Zen 5. And it looks like ARL will show little if any gain in gaming, based on the minimal single thread gains and possible increased latency due to the tiled design.

 

[AcrosTinus]

Lets not forget all the mitigations coming for RL and RL-R to mitigate the instability issues. They will be lucky to maintain parity with Zen 4, much less Zen 5. And it looks like ARL will show little if any gain in gaming, based on the minimal single thread gains and possible increased latency due to the tiled design.

These overblown stability issues will be solved via profile that one can adopt or not. For 14900K to lose against vanilla zen4, nearly 15 to 20% performance has to be lost.
This will never happen.

 

[desrever]

If 3% single thread improvement is true, it would be really LOL. And people were trashing 15% for Zen 5.

Even the e-cores seem really terrible based on the multithreaded score and using 250W. So much power for such a modest improvement on 3nm.