The next best reason is to be able to make such a product as SPR, Ponte Vecchio and a 64c to 96c EPYC at all. Just use any of the publicly available yield calculators (like
this one) and compare the good die percentage at a given defect rate for 400mm2 vs. 1600mm², or 70mm² vs. 560mm², or 40mm² vs. 640mm². Either the Reticle Limit strikes or the cost due to bad yields. And we are not talking about 20% more or less.
Furthermore you can employ cheaper processes for things that scale badly (IO, cache). And for Intel it is hopefully speeding up the time to market for Intel4 as they only need libraries for the compute dies and not the full feature set. But even if: Doing a monolithic die several times the size of the compute die on a an early process such as Intel4 where yields might be rather mediocre would quite likely be more expensive than the tiled approach. Example calculation for MTL:
- Let's say Intel can produce the 41mm² compute-die at Intel4 with a yield of 80% (which would be quite good in the beginning)
- The whole monolithic MTL might be around 150mm² due to limited scaling of IO and other blocks
- They would get 1181 good dies from a 300mm wafer for the compute-die alone
- For the monolithic one the yield would decrease to only 46% and only 179 good dies.
- So in this case the monolith costs them almost 7x more than the compute-die - although the size difference is only 3.7 times. So if the total costs of the other dies + packaging is less than that huge difference it becomes worth it. And as the other dies are small as well and/or on mature processes this is highly likely to me.
- Needless to say that the capacity for Intel4 might be severely constrained in the beginning.
I don't know enough about the detailed breakdown of the cost involved in monolithic vs big chiplet vs small chiplet. Common sense tells me that there is always a sweet spot and it is never at an extreme. As I said earlier, I don't think anyone with a sane mind will build a single core chiplet and put them on an interposer and think that they will have better economics and/or performance.
What I'm saying is that, from where I'm standing (10,000Km above sea level), SPL & PV seems to be a knee-jerk reaction to chiplet revolution that came too quickly for Intel. SPL seems to me like a rushed design. They just broke up their big monolithic design into 4 pieces and hoped EMIB would save them. PV went even further and broke up into more pieces when GPU is even harder to break up into chiplets due to high bandwidth requirements. There is a reason why NVidia builds the biggest chips in the world for their high-end GPU. Even AMD's chipet-based Navi31 is rumored to be 1 main die + memory controller die. No one has ever developed a GPU with chiplet approach and Intel thought that they can be the first one to build it and succeed...
MTL is better compared to SPL & PV, in terms of how the design is broken up into funtional units. It seems they did proper partitioning of the functional units. I'm sure it will be a good product for the intended market. Of the three main markets, AMD & Intel competes in (Mobile/Desktop/Server), MTL will be most competitive against AMD's products in its target market. But you have to realize that AMD is not building a product specifically for that market. AMD's desktop products have been derivatives of their server & mobile market products. Quite frankly, I'm surprised that AMD competes as well as it does in the desktop market when the products they introduce there are derivatives from their server market products.
The most important point I'm learning from MTL is that they chose to use a silicon interposer. That tells me that they are giving up on EMIB and EMIB has contributed to SPR & PV's troubles in a major way. Of course, it's my speculation. But I think it's a reasonable one. I don't expect to see EMIB in Intel's high-end products again anytime soon. Emerald Rapids, which keeps SPR's tile approach, will not be competitive against AMD"s products either. I don't know much about products after EMR, but Intel won't be competitive against AMD for at least 2 years. Their CEO said so himself and I believe him this time.
There are several theories about the problems doing their rounds, but to my knowledge the packaging has so far not been a major one.
I was also quite surprised they would not use EMIB. But 22nm seems to make this very cheap and maybe their older factories would otherwise face low demand.
You can build EMIB using the same 22nm silicon and use less of it. MTL proves, at least to me, that they are giving up on EMIB and most of their products that uses EMIB heavily (SPR/EMR/PV etc.) won't be competitive.
Right, and were is the problem to have both - EFB for chiplet connection and SoIC for Cache?
Cost and complexity. Transitor scaling has done wonders for semiconductor industry because cost & complexity in process technology increases linearly but the benefits increase exponentially. When you are manufacturing at large scale as semiconductor industry does, the exponential benefit will always win out. Development in packaging technology however, yields linear benefits in terms of production scale. So, you can't scale it as fast as fabrication technology and need to use it only when it makes sense.
In due time, when they built enough packaging facility we will see packaging technology used more widely. But it won't scale like fab technology, which increases transistor counts exponentially every few years.
MTL starts at 10w which already is low power. Apple also already uses Chiplets for Mobile (edit: Actually this is wrong.). Smart Phone SoCs are THE extreme. These surely will be the last ones to migrate - but in the long term also in this segment doing monoliths might become cost-prohibitive.
All in all I think you overestimate the costs of advanced packaging - this is a business with an astonishing growth rate and a lot of economics of scale to be gained. And on the other side you seem to underestimate the rising costs of monolithic dies on advanced processes with lesser and lesser scaling for everything that is not logic. But time will tell - and I think it will be interesting times from a technological perspective
I have to say that I disagree and, hopefully, I explained my reasons well enough above. Advanced packaging technology will be used to build high-end products that is not possible to build using traditional approach. Not to build mainstream products more cheaply. At least for a while.